US 7,067,379 B2 · Silicide gate transistors and method of manufacture

Abstract

A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.

Claims25

Dependent claims

A method of fabricating a transistor, comprising:

providing a semiconductor substrate comprised of a semiconductor layer formed on an insulator layer, the semiconductor substrate having a gate dielectric layer formed thereon and a gate electrode on said gate dielectric layer;
said gate electrode having two sides on which spacers are formed and a top surface;
forming source/drain regions adjacent to said spacers;
depositing a first metal layer on the source/drain regions and performing a first silicidation to form fully silicided source/drain regions;
covering the fully silicided source/drain regions with a dielectric layer;
depositing a second metal layer on the gate electrode and performing a second silicidation to form a fully silicided gate electrode.

3 more elements

A method of fabricating an NMOS transistor adjacent to a PMOS transistor, comprising:

providing a semiconductor substrate comprised of a semiconductor layer formed on an insulator layer, the semiconductor substrate having isolation regions that define a first active region comprised of a channel region with a p-type dopant and a second active region comprised of a channel region with an n-type dopant adjacent to said first active region;
forming a gate dielectric layer and an overlying first gate electrode on the first active region and a gate dielectric layer and an overlying second gate electrode on the second active region;
forming a first set of spacers adjacent to said first gate electrode and a second set of spacers adjacent to said second gate electrode;
forming a second semiconductor layer on the substrate that is coplanar with the top of the first gate electrode and the second gate electrode and selectively removing the second semiconductor layer over the isolation regions;
etching back the second semiconductor layer, first gate electrode, and second gate electrode to form a recessed first gate electrode, a recessed second gate electrode, raised first source/drain regions adjacent to the first set of spacers, and raised second source/drain regions adjacent to the second set of spacers;
selectively forming a first metal layer on the second active region and performing a first silicidation to form a fully silicided recessed second gate electrode and fully silicided raised second source/drain regions.
selectively forming a second metal layer over said first active region and performing a second silicidation to form a fully silicided recessed first gate electrode and fully silicided raised first source/drain regions.

4 more elements

Dependencies are inferred from the claim text.

Silicide gate transistors and method of manufacture

Life of this patent

Silicide gate transistors and method of manufacture

Life of this patent

Abstract

Claims25