Recessed channel with separated ONO memory device
AssigneeFasl LLC
InventorsJaeyong Park, Hidehiko Shiraiwa, Satoshi Torii, Mark T. Ramsbey
Life of this patent
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Abstract
Systems and methods of fabricating a U-shaped memory device with a recessed channel and a segmented/separated ONO layer are provided. Multibit operation is facilitated by a separated ONO layer, which includes a charge trapping region on sidewalls of polysilicon gate structures adjacent to source/drain regions. Programming and erasing of the memory cells is facilitated by the relatively short distance between acting source regions and the gate. Additionally, short channel effects are mitigated by a relatively long U-shaped channel region that travels around the recessed polysilicon gate thereby adding a depth dimension to the channel length.
Claims18
A method of fabricating a memory device with a recessed channel comprising:
- selectively etching trenches in a semiconductor substrate;
- forming an oxide layer within at least the trenches;
- depositing a first conductive layer over the semiconductor substrate and in the trenches;
- planarizing the device to selectively remove portions of the first conductive layer while leaving portions of the first conductive layer in the trenches to form gates;
- performing one or more bitline implants to form bitlines adjacent to the gates;
- removing portions of the oxide layer located in the trenches adjacent to the gates to a first depth defining gap regions;
- partially filling the gap regions with a lower insulating layer;
- depositing a charge trapping material within at least the gap regions on the lower insulating layer;
- and
- forming an upper insulating layer on the deposited charge trapping material.
A method of fabricating a memory device with a recessed channel comprising:
- selectively etching trenches in a semiconductor substrate;
- forming an insulating layer within at least the trenches;
- depositing a first conductive layer over the semiconductor substrate and in the trenches;
- selectively removing portions of the first conductive layer while leaving portions of the first conductive layer in the trenches to form gates;
- performing one or more bitline implants to form bitlines adjacent to the gates;
- removing portions of the insulating layer located in the trenches adjacent to the gates to a first depth defining gap regions;
- partially filling the gap regions with an insulating material;
- removing the insulating material from the gap regions and an additional amount of the insulating layer remaining in the trenches to expand the gap regions to a second depth that is greater than the first depth;
- forming a lower insulating layer in at least the gap regions;
- depositing a charge trapping material within at least the gap regions on the lower insulating layer;
- and
- forming an upper insulating layer on the deposited charge trapping material.
A method of fabricating a memory device with a recessed channel comprising:
- forming shallow trench isolation regions in a semiconductor substrate within a periphery region of the device;
- selectively etching core trenches in a semiconductor substrate within a core region of the device;
- forming an insulating layer within at least the core trenches;
- depositing a first conductive layer over the semiconductor substrate and in the trenches;
- selectively removing portions of the first conductive layer while leaving portions of the first conductive layer in the trenches to form gates within the core region;
- performing a bitline implant to form bitlines within the core region adjacent to the gates;
- selectively forming well regions within the periphery region;
- removing portions of the insulating layer located in the trenches adjacent to the gates to a first depth defining gap regions;
- partially filling the gap regions with a lower insulating layer;
- depositing a charge trapping material within at least the gap regions on the lower insulating layer;
- and
- forming an upper insulating layer on the deposited charge trapping material.
Dependencies are inferred from the claim text.