US 7,067,376 B2Granted

High voltage power MOSFET having low on-resistance

AssigneeGeneral Semiconductor, Inc.

InventorRichard A. Blanchard

Life of this patent

Estimating the term…

Loading patent…

Abstract

A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with an epitaxially layered material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.

Claims13

Dependent claims

A method of forming a power MOSFET comprising the steps of:

providing a substrate of a first conductivity type;
depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;
forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type;
forming first and second source regions of the first conductivity type in the first and second body regions, respectively;
and
forming a plurality of trenches in said drift region of the epitaxial layer;
epitaxially depositing in said trenches a material having a dopant of the second conductivity type, said trenches extending toward the substrate from the first and second body regions;
and
diffusing at least a portion of said dopant from said trenches into portions of the epitaxial layer adjacent the trenches;
said epitaxially deposited material filling the trench includes silicon;
and further comprising the step of forming a layer of dielectric on the epitaxially deposited material filling the trench.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/673,889Filed 29 Sep 2003 · division
Priority: 2 Jun 2000
Published: US 2004/0070044 A115 Apr 2004
Granted: 27 Jun 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 30/66
Double-diffused metal-oxide semiconductor [DMOS] FETs: vertical dmos [vdmos] fets
H10D 30/0291
Of double-diffused metal oxide semiconductor [DMOS] FETs: of vertical dmos [vdmos] fets
H10D 62/058
Forming charge compensation regions, e.g. superjunctions: by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches
H10D 62/111
Reduced surface field [RESURF] PN junction structures: multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures

Family

Application09/586,407Parent of this continuation-in-part · filed 2 Jun 2000
Application09/849,036Parent of this division · filed 4 May 2001
US 2004/0070044 A1Pre-grant publication · published 15 Apr 2004
US 6,627,949 B2Parent of this division
US 6,593,619 B1Parent of this continuation-in-part
Application09/849,036Parent of this continuation-in-part
US 2002/0014658 A1Published application
US 7,067,376 B2This patent

From the US filing history. Foreign family members aren’t listed.