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US 7,067,373 B2Granted

Semiconductor integrated circuit device and a method of manufacturing the same

AssigneeRenesas Technology Corp.

InventorShoji Shukuri

Life of this patent

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Abstract Drawings Claims Description

Abstract

The present invention provides a semiconductor integrated circuit device capable of reading memory information from an on-chipped nonvolatile memory cell transistor at high speed. The memory cell transistor includes, in a first well region, a pair of memory electrodes of which one serves as a source electrode and the other serves as a drain electrode, and a channel region interposed between the pair of memory electrodes, and includes, on a channel region, a first gate electrode disposed near its corresponding memory electrode with an insulating film interposed therebetween, and a second gate electrode disposed through insulating films and a charge storage region and electrically isolated from the first gate electrode. A first negative voltage is applied to the first well region to form a state of a reverse bias greater than or equal to a junction withstand voltage between the second gate electrode and the memory electrode near the second gate electrode, thereby enabling injection of hot electrons into the charge storage region and injection of electrons from the well region to the charge storage region.

Claims80

Dependent claims

Claim 1A method of manufacturing a semiconductor integrated circuit device · 164 words6 dependent Claim 7A method of manufacturing a semiconductor integrated circuit device · 133 words4 dependent Claim 12A method of manufacturing a semiconductor integrated circuit device · 128 words3 dependent Claim 17A method of manufacturing a semiconductor integrated circuit device · 162 words5 dependent Claim 19A method of manufacturing a semiconductor integrated circuit device · 209 words5 dependent Claim 21A method of manufacturing a semiconductor integrated circuit device · 258 words4 dependent Claim 28A method of manufacturing a semiconductor integrated circuit device · 169 words4 dependent Claim 31A method of manufacturing a semiconductor integrated circuit device · 179 words4 dependent Claim 34A method of manufacturing a semiconductor integrated circuit device · 250 words4 dependent Claim 35A method of manufacturing a semiconductor integrated circuit device · 251 words4 dependent Claim 40A method of manufacturing a semiconductor integrated circuit device · 160 words3 dependent Claim 43A method of manufacturing a semiconductor integrated circuit device · 180 words2 dependent Claim 53A method of manufacturing a semiconductor integrated circuit device · 137 words4 dependent Claim 57A method of manufacturing a semiconductor integrated circuit device · 203 words4 dependent Claim 61A method of manufacturing a semiconductor integrated circuit device · 207 words4 dependent Claim 65A method of manufacturing a semiconductor integrated circuit device · 199 words4 dependent

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first conductive film over a memory cell forming region and a peripheral circuit forming region of a semiconductor substrate;
patterning said first conductive film in said memory cell forming region to form a first conductor pattern which serves as a first gate electrode of a memory cell;
forming a second conductive film over said memory cell forming region and over said first conductive film in said peripheral circuit forming region;
etching said second conductive film to form a second gate electrode of said memory cell on at least side surface of said first conductor pattern, and to form an electrode structure of a peripheral circuit element comprising said second conductive film and first conductive film in said peripheral circuit forming region;
and
forming a first silicide layer on said first gate electrode of said memory cell and a second silicide layer on said second gate electrode of said memory cell.

3 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first conductive film over a memory cell forming region of a semiconductor substrate and forming an insulating film over said first conductive film;
etching said insulating film and said first conductive film to form a first conductor pattern which serves as a first gate electrode of a memory cell;
forming a second gate electrode of said memory cell on side walls of said first conductor pattern;
removing said insulating film over said first conductor pattern;
forming sidewall spacers, each comprised of an insulating film, in self-alignment with side walls of said second gate electrode;
and
forming a silicide layer for each of said first conductor pattern and said second gate electrode in self-alignment with respect to said sidewall spacers.

4 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first conductive film over a memory cell forming region of a semiconductor substrate and forming an insulating film on said first conductive film;
etching said insulating film and said first conductive film to form a first conductor pattern which serves as a first gate electrode of a memory cell;
forming a second gate electrode of said memory cell on side walls of said first conductor pattern;
removing said insulating film over said first conductor pattern;
forming sidewall spacers, each comprised of an insulating film, in self-alignment with side walls of said second gate electrode;
and
etching said first conductor pattern in self-alignment with respect to said sidewall spacers to form corresponding first gate electrode.

4 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first conductive film into a first conductor pattern which serves as a first gate electrode of a memory cell over a memory cell forming region of a semiconductor substrate;
forming an insulator film over side surface of said first conductor pattern and over said memory cell forming region;
forming a second conductive film over said memory cell forming region and said insulator film;
etching said second conductive film to form a second gate electrode of said memory cell on at least side surface of said first conductor pattern;
forming a sidewall spacer of an insulator material in self-alignment with side walls of said second gate electrode;
and
forming a first silicide layer on said first gate electrode of said memory cell and a second silicide layer on said second gate electrode of said memory cell,
wherein said first silicide layer and said second silicide layer are electrically separated.

5 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first conductive film into a first conductor pattern which serves as a first gate electrode of a memory cell over a memory cell forming region of a semiconductor substrate;
forming an insulator film over side surfaces of said first conductor pattern and over said memory cell forming region;
forming a second conductive film over said memory cell forming region and said insulator film;
etching said second conductive film to form a second conductor pattern in self-alignment with said surface of said first conductor pattern such that said second conductor pattern has a shape of a sidewall spacer;
removing said second conductor pattern to form a second gate electrode of said memory cell on one side of said side surfaces of said first conductor pattern;
forming sidewall spacers of an insulator material in self-alignment with side walls of said second gate electrode and in self-alignment with said side surface of said first gate electrode;
and
forming a first silicide layer on said first gate electrode of said memory cell and a second silicide layer on said second gate electrode of said memory cell,
wherein said first silicide layer and said second silicide layer are electrically separated.

6 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first conductive film over a memory cell forming region and a peripheral circuit forming region of a semiconductor substrate;
patterning said first conductive film in said memory cell forming region so as to form a first conductor pattern which serves as a first gate electrode of a memory cell;
forming an insulator film over side surface of said first conductor pattern and over said memory cell forming region;
forming a second conductive film over said memory cell forming region and said insulator film;
etching said second conductive film to form a second conductor pattern, serving as a second gate electrode of said memory cell, in self-alignment with said first conductor pattern such that said second conductor pattern has a shape of a side wall spacer;
forming a gate electrode of a peripheral circuit transistor by patterning said first conductive film in said peripheral circuit forming region;
forming sidewall spacers of an insulator material in self-alignment with side walls of said second gate electrode, in self-alignment with said side surface of said first gate electrode and in self-alignment with side surfaces of said gate electrode of said peripheral circuit transistor;
and
forming a first silicide layer on said first gate electrode of said memory cell, a second silicide layer on said second gate electrode of said memory cell and a third silicide layer on said gate electrode of said peripheral circuit transistor,
wherein said first silicide layer and said second silicide layer are electrically separated.

7 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first conductor pattern which serves as a first gate electrode of a memory cell over a memory cell forming region of a semiconductor substrate;
forming an insulator film over side surface of said first conductor pattern and over said memory cell forming region;
forming a second gate electrode of said memory cell in self-alignment with said side surface of said first conductor pattern such that said second gate electrode has a shape of a sidewall spacer and such that said insulator film is formed between said first conductor pattern and said second gate electrode;
forming a side wall spacer of an insulator material in self-alignment with side walls of said second gate electrode;
and
forming a first silicide layer on said first gate electrode of said memory cell and a second silicide layer on said second gate electrode of said memory cell,
wherein said first silicide layer and said second silicide layer are electrically separated.

4 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first conductor pattern which serves as a first gate electrode of a memory cell over a memory cell forming region of a semiconductor substrate;
forming an insulator film over side surface of said first conductor pattern and over said memory cell forming region;
selectively forming a second gate electrode of said memory cell in self-alignment with one side surface of said first conductor pattern such that said second gate electrode has a shape of a sidewall spacer and such that said insulator film is formed between said first conductor pattern and said second gate electrode;
forming sidewall spacers of an insulator material in self-alignment with side walls of said second gate electrode, in self-alignment with other side surface of said first conductor pattern;
and
forming a first silicide layer on said first gate electrode of said memory cell and a second silicide layer on said second gate electrode of said memory cell,
wherein said first silicide layer and said second silicide layer are electrically separated.

4 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first conductive film over a memory cell forming region and a peripheral circuit forming region of a semiconductor substrate;
patterning said conductive film in said memory cell forming region to form a first conductor pattern which serves as a first gate electrode of a memory cell;
forming an insulator film over side surface of said first conductor pattern and over said memory cell forming region;
forming a second gate electrode of said memory cell in self-alignment with said side surface of said first conductor pattern such that said second gate electrode has a shape of a side wall spacer and such that said insulator film is formed between said first conductor pattern and said second gate electrode;
forming a gate electrode of a peripheral circuit transistor by patterning said first conductive film in said peripheral circuit forming region;
forming sidewall spacers of an insulator material in self-alignment with side walls of said second gate electrode, in self-alignment with said side surfaces of said first gate electrode and in self-alignment with side surfaces of said gate electrode of said peripheral circuit transistor;
and
forming a first silicide layer on said first gate electrode of said memory cell, a second silicide layer on said second gate electrode of said memory cell and a third silicide layer on said gate electrode of said peripheral circuit transistor,
wherein said first silicide layer and said second silicide layer are electrically separated.

6 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first conductive film over a memory cell forming region and a peripheral circuit forming region of a semiconductor substrate;
patterning said conductive film in said memory cell forming region to form a first conductor pattern which serves as a first gate electrode of a memory cell;
forming an insulator film over side surface of said first conductor pattern and over said memory cell forming region;
selectively forming a second gate electrode of said memory cell in self-alignment with one side surface of said first conductor pattern such that said second gate electrode has a shape of a sidewall spacer and such that said insulator film is formed between said first conductor pattern and said second gate electrode;
forming a gate electrode of a peripheral circuit transistor by patterning said first conductive film in said peripheral circuit forming region;
forming sidewall spacers of an insulator material in self-alignment with said side walls of said second gate electrode, in self-alignment with other side surface of said first conductor pattern and in self-alignment with side surfaces of said gate electrode of said peripheral circuit transistor;
and
wherein said first silicide layer and forming a first silicide layer on said first gate electrode of said memory cell, a second silicide layer on said second gate electrode of said memory cell and a third silicide layer on said gate electrode of said peripheral circuit transistor,
said second silicide layer are electrically separated.

6 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first gate electrode of a memory cell over a memory cell forming region of a semiconductor substrate;
forming an insulator film over side surface of said first gate electrode and over said memory cell forming region;
forming a second gate electrode of said memory cell in self-alignment with said side surface of said first gate electrode such that said second gate electrode has a shape of a sidewall spacer and such that said insulator film is formed between said first gate electrode and said second gate electrode;
forming a sidewall spacer of an insulator material in self-alignment with side walls of said second gate electrode;
forming a first silicide layer on said first gate electrode of said memory cell and a second silicide layer on said second gate electrode of said memory cell,
wherein said first silicide layer and said second silicide layer are electrically separated.

3 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first gate electrode of a memory cell over a memory cell forming region of a semiconductor substrate;
forming an insulator film over side surface of said first gate electrode and over said memory cell forming region;
forming a second gate electrode of said memory cell in self-alignment with said side surface of said first gate electrode such that said second gate electrode has a shape of a sidewall spacer and such that said insulator film is formed between said first gate electrode and said second gate electrode;
forming a sidewall spacer of an insulator material in self-alignment with side walls of said second gate electrode;
and
forming a first silicide layer on said first gate electrode of said memory cell and a second silicide layer on said second gate electrode of said memory cell,
wherein a height of said first gate electrode is different from a height of said second gate electrode, and
wherein said first silicide layer and said second silicide layer are electrically separated.

5 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first gate electrode of a memory cell over a memory cell forming region of a semiconductor substrate;
forming an insulator film over one of side surfaces of said first gate electrode and over said memory cell forming region;
forming a second gate electrode of said memory cell in self-alignment with said one of side surfaces of said first gate electrode such that said second gate electrode has a shape of a sidewall spacer and such that said insulator film is formed between said first gate electrode and said second gate electrode;
and
forming sidewall spacers of an insulator material in self-alignment with side walls of said second gate electrode and in self-alignment with other of said side surfaces of said first gate electrode.

2 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first gate electrode of a memory cell over a memory cell forming region of a semiconductor substrate;
forming an insulator film over side surface of said first gate electrode and over said memory cell forming region;
forming a second gate electrode of said memory cell in self-alignment with said side surface of said first gate electrode such that said second gate electrode has a shape of a sidewall spacer and such that said insulator film is formed between said first gate electrode and said second gate electrode;
forming a gate electrode of a peripheral circuit transistor in a peripheral circuit forming region;
forming sidewall spacers of an insulator material in self-alignment with side walls of said second gate electrode and in self-alignment with side surfaces of said gate electrode of said peripheral circuit transistor;
and
forming a first silicide layer on said first gate electrode of said memory cell, a second silicide layer on said second gate electrode of said memory cell and a third silicide layer on said gate electrode of said peripheral circuit transistor,
wherein said first silicide layer and said second silicide layer are electrically separated.

5 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first gate electrode of a memory cell over a memory cell forming region of a semiconductor substrate;
forming an insulator film over one of side surfaces of said first gate electrode and over said memory cell forming region;
forming a second gate electrode of said memory cell in self-alignment with said one of side surfaces of said first gate electrode such that said second gate electrode has a shape of a sidewall spacer and such that said insulator film is formed between said first gate electrode and said second gate electrode;
forming a gate electrode of a peripheral circuit transistor in a peripheral circuit forming region;
forming sidewall spacers of an insulator material in self-alignment with side walls of said second gate electrode and in self-alignment with side surfaces of said gate electrode of said peripheral circuit transistor;
and
forming a first silicide layer on said first gate electrode of said memory cell, a second silicide layer on said second gate electrode of said memory cell and a third silicide layer on said gate electrode of said peripheral circuit transistor,
wherein said first silicide layer and said second silicide layer are electrically separated.

5 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising steps of:

forming a first conductor pattern serving as a gate electrode of a memory cell over a memory cell forming region of a semiconductor substrate and a second conductor pattern over a peripheral circuit forming region of said substrate;
forming an insulator film over side surface of said first gate electrode and over said memory cell forming region;
forming a second gate electrode of said memory cell in self-alignment with said side surface of said first gate electrode such that said second gate electrode has a shape of a sidewall spacer and such that said insulator film is formed between said first gate electrode and said second gate electrode,
wherein in said second gate electrode forming step, a third conductor pattern is formed over said second conductor pattern,
forming side wall spacers of an insulator material in self-alignment with side walls of said second gate electrode;
and
forming a first silicide layer on said first gate electrode of said memory cell and a second silicide layer on said second gate electrode of said memory cell,
wherein said first silicide layer and said second silicide layer are electrically separated.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/767,069Filed 30 Jan 2004 · continuation in part
Priority: JP 2002-11592418 Apr 2002
Published: US 2004/0185617 A123 Sep 2004
Granted: 27 Jun 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification32 codes

H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region
B82Y 10/00
Nanotechnology for information processing, storage or transmission
G11C 16/0466
Using variable threshold transistors, e.g. FAMOS: comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon…
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits

Family

Application10/400,469Parent of this continuation-in-part · filed 28 Mar 2003
US 2004/0185617 A1Pre-grant publication · published 23 Sep 2004
US 2003/0198086 A1Published application
US 7,045,848 B2Related patent
US 7,067,373 B2This patent

From the US filing history. Foreign family members aren’t listed.

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