Method of manufacturing a MOS transistor of a semiconductor device

A method of forming a transistor of a semiconductor device comprising:

• forming an N type gate pattern and a P type gate pattern on an N type transistor area and a P type transistor area, respectively, of a semiconductor substrate;
• forming an oxide layer on the substrate including the N type gate pattern and the P type gate pattern to repair damage to the substrate and the gate patterns after forming the N type gate pattern and the P type gate pattern;
• selectively implanting N type impurities into the N type transistor area;
• forming an insulation layer on the substrate including the N type gate pattern and the P type gate pattern;
• forming a first spacer on sidewalls of the P type gate pattern by anisotropically etching a portion of the insulation layer in the P type transistor area while a portion of the insulation layer remains in the N type transistor area;
• and
• selectively implanting P type impurities into the P type gate pattern including the first spacer and into the P type transistor area.

A method of forming a transistor of a semiconductor device comprising:

• forming an N type gate pattern and a P type gate pattern on an N type transistor area and a P type transistor area, respectively, of a semiconductor substrate;
• selectively implanting N type impurities into the N type transistor area;
• forming an insulation layer on the substrate including the N type gate pattern and the P type gate pattern;
• forming a first spacer on sidewalls of the P type gate pattern by anisotropically etching a portion of the insulation layer in the P type transistor area while a portion of the insulation layer remains in the N type transistor area;
• selectively implanting P type impurities into the P type gate pattern including the first spacer and into the P type transistor area;
• selectively removing the portion of the insulation layer in the N type transistor area and selectively removing the first spacer on the P type transistor region;
• forming second spacers on sidewalls of the N type gate pattern and the P type gate pattern;
• selectively implanting N type impurities into the N type gate pattern and into the N type transistor area;
• and
• selectively implanting P type impurities into the P type gate pattern and into the P type transistor area.

A method of forming a transistor of a semiconductor device comprising:

• forming an N type gate pattern and a P type gate pattern on an N type transistor area and a P type transistor area, respectively, of a semiconductor substrate, wherein each of the gate patterns includes a gate oxide layer pattern and an undoped polysilicon layer pattern;
• forming a thermal oxidized layer on the substrate including the gate patterns to repair damage to the substrate and the gate patterns;
• selectively implanting N type impurities into the N type gate patterns and into a portion of the substrate adjacent to the N type gate pattern to change the undoped polysilicon layer pattern into a conductive polysilicon layer and to form an N type impurity region having a low impurity concentration adjacent to the N type gate pattern;
• forming an insulation layer on the substrate including the gate patterns;
• forming a first spacer on sidewalls of the P type gate pattern by anisotropically etching a portion of the insulation layer in the P type transistor area while a portion of the insulation layer remains in the N type transistor area;
• and
• selectively implanting P type impurities into the P type gate pattern and a portion of the substrate adjacent to the P type gate pattern to change the undoped polysilicon layer pattern into a conductive polysilicon layer pattern and to form a P type impurity region having a low impurity concentration adjacent to the P type gate pattern.