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AssigneeInternational Business Machines Corporation
InventorRainer E. Gehres
Estimating the term…
A method is provided for defining spacings between the gates of field effect transistors (FETs) of an integrated circuit and the source and drain regions thereof, the spacings differing in width between a first FET and a second FET. The method includes forming gate stacks of the integrated circuit over a substrate, and forming first spacers on sidewalls of the gate stacks. Second spacers are then formed over the first spacers. Thereafter, source and drain regions of the first FET are formed in alignment with the second spacers of a first gate stack of the gate stacks. The second spacers are then removed from the first spacers of the gate stacks. Thereafter, the first spacers of a second gate stack are anisotropically etched in a substantially vertical direction to remove horizontally extending portions of the first spacers, and source and drain regions of the second FET are formed in alignment with portions of the first spacers of the first gate stack which remain after the etching.
A method of fabricating first and second field effect transistors (FETs) of an integrated circuit such that said first FET has different spacings between the gate and the source and drain regions thereof than said second FET, comprising:
Dependencies are inferred from the claim text.
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Manufacture or treatment: removing at least parts of gate spacers, e.g. disposable spacers
Of FETs having insulated gates [IGFET]: using self-aligned silicidation
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
Term ended 5 Apr 2024 (estimated)
The invention relates to semiconductor manufacturing processes, and more particularly to a method of making field effect transistors having source and drain regions self-aligned to the gates thereof.
In fabrication of complementary metal oxide semiconductor (CMOS) integrated circuits, gate sidewall spacers are sometimes used to control the spacing between the source and drain regions of field effect transistors (FETs) and the gates of the FETs. Typically in such process, source and drain doping is performed by ion implantation into a semiconductor substrate, using the gate stack and one or more spacers formed on sidewalls of the gate stack as a mask.
Many integrated circuits (“ICs” or “chips”) include both n-type FETs (NFETs) and p-type FETs (PFETs), such as integrated circuits having complementary metal oxide semiconductor (CMOS) technology, but non-CMOS technology chips such as NMOS chips often incorporate PFETs as well. For best performance, it is sometimes desirable or necessary for the source and drain regions of a PFET to be spaced a different distance from the gate of the PFET than is the case for an NFET on the same chip. The source and drain regions may either be spaced farther away from the gate in the PFET than in the NFET or, alternatively, closer to the gate.
FIG. 1A is a top down view illustrating processing to define gate sidewall spacers having different widths in particular FETs according to a method which is background to the present invention;
FIG. 1B is a top down view illustrating processing to define gate sidewall spacers having different widths in particular FETs according to an embodiment of the invention; and
FIGS. 2 through 12 illustrate stages in processing according to embodiments of the invention.
Accordingly, a method is provided according to the present invention in which the widths of gate sidewall spacers are made different for respective FETs of the chip. Improved process window is provided by virtue of using a vertical etch process to define the areas in which the respective FETs are formed.
In an embodiment of the invention shown in FIG. 1B, an NFET 102 and a PFET 104 are provided in active areas 140 of a single-crystal semiconductor region of a substrate. The substrate is preferably a semiconductor-on-insulator substrate such as a silicon-on-insulator (SOI) substrate, although, a bulk semiconductor substrate can be alternatively used. When field effect transistors (FETs) are formed in SOI substrates, faster switching operation is often achieved than otherwise, because junction capacitance between the channel region of the transistor and the bulk substrate is eliminated.
The embodiment shown in FIG. 1B is similar to that shown in FIG. 1A, with the exception that the boundary between the thin spacer 172 in the NFET 102 and the thicker spacer 170 in the PFET 104 is more sharply defined, by the boundary 175 of a masking layer 180. Compared to the background process described in FIG. 1A in which a small overlay tolerance 52 is provided, a larger overlay tolerance 62 results from this process.