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US 7,067,365 B1Granted
High-voltage metal-oxide-semiconductor devices and method of making the same
AssigneeUnited Microelectronics Corp.
InventorsWen-Fang Lee, Wei-Lun Hsu, Yu-Hsien Lin
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Abstract
An improved high-voltage process is disclosed. In order to improve the performance in terms of breakdown voltage and to maintain the integrity of the STI structures, the thick gate oxide layer of the high-voltage device area is not etched back before a high-dosage ion doping process. One photo mask is therefore omitted.
Claims13
A method of fabricating a high-voltage metal-oxide-semiconductor (MOS) device, comprising the steps of:
- providing a semiconductor substrate comprising a high-voltage device area thereon and shallow trench isolation (STI) structure that further divides said high-voltage device area into a first sub-area and a second sub-area;
- implanting ions into said semiconductor substrate within said high-voltage device area to form a first doping region and a second doping region with a channel region defined therebetween;
- forming a pad oxide layer on said semiconductor substrate;
- depositing a pad nitride layer on said pad oxide layer;
- forming an opening in said pad nitride layer and said pad oxide layer, wherein said opening merely exposes a portion of said first sub-area of said high-voltage device area including said channel region;
- growing a first oxide layer on exposed said semiconductor substrate via said opening;
- stripping off remaining said pad nitride layer and said pad oxide layer;
- growing a second oxide layer on said first sub-area and on said second sub-area;
- forming a gate on said first oxide layer;
- and
- performing an ion implantation process, using said gate and said first oxide layer as an implant mask, to form a third doping region within said first doping region and a fourth doping region within said second doping region.
8 more elements
A method of fabricating a high-voltage N-type metal-oxide-semiconductor (NMOS) device, comprising the steps of:
- providing a semiconductor substrate comprising a high-voltage device area thereon and shallow trench isolation (STI) structure that further divides said high-voltage device area into a first sub-area and a second sub-area;
- implanting ions into said semiconductor substrate within said high-voltage device area to form a first N-grade doping region and a second N-grade doping region with a channel region defined therebetween;
- forming a mask layer on said semiconductor substrate;
- forming an opening in said mask layer, wherein said opening merely exposes a portion of said first sub-area of said high-voltage device area including said channel region;
- growing a first oxide layer on exposed said semiconductor substrate via said opening;
- stripping off remaining said mask layer;
- growing a second oxide layer on said first sub-area and on said second sub-area;
- forming a gate on said first oxide layer;
- and
- performing an ion implantation process, using said gate and said first oxide layer as an implant mask, to form a first N+ doping region within said first N-grade doping region and a second N+ doping region within said second N-grade doping region.
7 more elements
Dependencies are inferred from the claim text.