Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density

A method for forming a semiconductor device comprising:

• forming spaced apart active areas in a semiconductor substrate and defining a JFET area therebetween, the JFET area also forming a channel between the source and drain areas;
• forming a gate oxide on the semiconductor substrate and comprising a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area, the second thickness being greater than the first thickness, wherein forming the gate oxide comprises
• forming an oxide pad on the active areas and on the channel,
• forming a polysilicon layer having a thickness less than or equal to one-half the second thickness of the second portion of the gate oxide,
• forming a nitride layer on the polysilicon layer,
• forming a photoresist layer on the nitride layer except over a portion of the JFET area corresponding to the second portion of the gate oxide,
• removing the exposed nitride layer,
• implanting dopants through the exposed polysilicon layer while using the photoresist layer as an implant window for forming the enrichment region in the JFET area,
• removing the photoresist layer,
• oxidizing the polysilicon layer not covered by the nitride layer, and
• removing the nitride layer;
• and
• forming a gate electrode on the first and second portions of the gate oxide.