Program development compressed trace support apparatus

A program development support apparatus comprising:

• a CPU (Central Processing Unit) for executing a target program and outputting instruction address/instruction code data;
• event management means for asserting and outputting a section trace start signal upon detecting that the instruction address/instruction code data from said CPU matches at least one of a predetermined instruction address and a predetermined instruction code set as an event condition in advance, the predetermined instruction code being different from a branch instruction;
• trace data generation means for;
• outputting an uncompressed instruction address as trace data when an instruction code of the instruction address/instruction code data from said CPU is a branch instruction;
• outputting the uncompressed instruction address as the trace data when the section trace start signal from said event management means is active;
• generating a plurality of compressed instruction addresses by compressing the instruction address of the instruction address/instruction code data, combining the compressed instruction addresses, and outputting the compressed instruction addresses as the trace data when the instruction address of the instruction address/instruction code data is not a branch instruction and the section trace start signal is not active;
• and
• a trace memory for storing the trace data from said trace data generation means.