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US 7,065,732 B1Granted
Method to reduce the power consumption of large PLAs by clock gating guided by recursive shannon decomposition of the and-plane
AssigneeIntel Corporation
InventorsVictor Konrad, Vivek Joshi
Life of this patent
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Abstract
A method that includes steps for determining an optimum splitting variable and dividing a programmable logic array (PLA) into a first sub-PLA and a second sub-PLA based on the splitting variable is presented. The method also provides for gating logic to be applied to the first sub-PLA and the second sub-PLA. Power consumption is then controlled in the first sub-PLA and the second sub-PLA so only one of the first sub-PLA and the second sub-PLA contributes to power consumption. In another embodiment, a PLA be recursively divided into a plurality of sub-PLAs.
Claims30
A method for applying partitioning logic to partially optimized programmable logic arrays comprising:
- determining an optimum splitting variable for dividing a programmable logic array (PLA) into at least two sub-PLAs by avoiding unbalanced columns in an AND plane of a set of equations representing the PLA;
- and selecting a column with smallest overhead in the AND plane of the set of equations representing the PLA, each sub-PLA of said at least two sub-PLAs having an AND plane and an OR plane, a first sub-PLA of said at least two sub-PLAs includes products in which said splitting variable is in complemented form, a second sub-PLA of said at least two sub-PLAs includes products in which said splitting variable is in uncomplemented form, said splitting variable corresponding to a specific input, output and product in the set of equations representing the PLA;
- dividing the set of equations representing the PLA into a first set of equations representing the first sub-PLA and a second set of equations representing the second sub-PLA based on the splitting variable;
- determining a topological circuit representation of the equations representing the first sub-PLA and the equations representing the second sub-PLA;
- applying gating logic to the topological circuit representation of the equations representing the first sub-PLA and the equations representing the second sub-PLA;
- and
- controlling power consumption in the topological circuit representation of the equations representing the first sub-PLA and the equations representing the second sub-PLA so only one of the topological circuit representation of the first sub-PLA and the second sub-PLA contributes to power consumption,
- wherein an OR plane of the topological circuit representation of the first sub-PLA is interleaved with an OR plane of the topological circuit representation of the second sub-PLA.
5 more elements
A method for applying partitioning logic to partially optimized programmable logic arrays comprising:
- determining an optimum splitting variable for dividing a set of equations representing a programmable logic array (PLA) into equations representing at least two sub-PLAs by avoiding unbalanced columns in an AND plane of the equations representing the PLA;
- and selecting a column with smallest overhead in the AND plane of the equations representing the PLA, each sub-PLA of said at least two sub-PLAs having an AND plane and an OR plane, a first sub-PLA of said at least two sub-PLAs includes products in which said splitting variable is in complemented form, a second sub-PLA of said at least two sub-PLAs includes products in which said splitting variable is in uncomplemented form, said splitting variable corresponding to a specific input, output and product in the set of equations representing the PLA;
- dividing the set of equations representing the PLA into equations representing the at least two sub-PLAs;
- merging outputs of the equations representing the at least two sub-PLAs;
- determining a topological circuit representation of the equations representing the at least two sub-PLAs;
- applying gating logic to the topological circuit representation of the at least two sub-PLAs;
- and
- controlling power consumption in the topological representation of the at least two sub-PLAs so only one of the at least two sub-PLAs contributes to power consumption,
- wherein an OR plane of the topological circuit representation of a first sub-PLA is one of interleaved and separated with an OR plane of the topological circuit representation of a second sub-PLA.
6 more elements
A program storage device readable by a machine comprising instructions that cause the machine to:
- determine an optimum splitting variable for dividing a programmable logic array (PLA) into a first sub-PLA and a second sub-PLA by avoiding unbalanced columns in an AND plane of a set of equations representing the PLA;
- and selecting a column with smallest overhead in the AND plane of the set of equations representing the PLA, said first sub-PLA and said second sub-PLA each have an AND plane and an OR plane, the first sub-PLA includes products in which said splitting variable is in complemented form, the second sub-PLA includes products in which said splitting variable is in uncomplemented form, said splitting variable corresponding to a specific input, output and product in the set of equations representing the PLA;
- divide the set of equations representing the PLA into a first set of equations representing the first sub-PLA and a second set of equations representing the second sub-PLA based on the splitting variable;
- determine a topological circuit representation of first sub-PLA and the second sub-PLA;
- apply gating logic to the topological circuit representation of the first sub-PLA and the second sub-PLA;
- and
- control power consumption in the topological circuit representation of the first sub-PLA and the second sub-PLA so only one of the first sub-PLA and the second sub-PLA contributes to power consumption,
- wherein the topological circuit representation an OR plane of the first sub-PLA is interleaved with an OR plane of the second sub-PLA.
5 more elements
A program storage device readable by a machine comprising instructions that cause the machine to:
- determine an optimum splitting variable for dividing a set of equations representing a programmable logic array (PLA) into equations representing at least two sub-PLAs by avoiding unbalanced columns in an AND plane of the equations representing the sub-PLA and selecting a column with smallest overhead in the AND plane of the equations representing the sub-PLA, each sub-PLA of said at least two sub-PLAs having an AND plane and an OR plane, a first sub-PLA of said at least two sub-PLAs includes products in which said splitting variable is in complemented form, a second sub-PLA of said at least two sub-PLAs includes products in which said splitting variable is in uncomplemented form, said splitting variable corresponding to a specific input, output and product in the set of equations representing the PLA;
- divide the set of equations representing the PLA into equations representing the at least two sub-PLAs;
- merge outputs of the equations representing the at least two sub-PLAs;
- determine a topological circuit representation of the equations representing the at least two sub-PLAs;
- apply gating logic to the topological circuit representation of the at least two sub-PLAs;
- and
- control power consumption in the topological circuit representation of the at least two sub-PLAs so only one of the at least two sub-PLAs contributes to power consumption,
- wherein an OR plane of the topological circuit representation of a first sub-PLA is one of interleaved and separated with an OR plane of the topological circuit representation of a second sub-PLA.
5 more elements
A method for applying partitioning logic to partially optimized programmable logic arrays comprising:
- determining an optimum splitting variable for dividing a programmable logic array (PLA) into a first sub-PLA and a second sub-PLA, said first sub-PLA and said second sub-PLA each having an AND plane and an OR plane by avoiding unbalanced columns in an AND plane of a set of equations representing the PLA;
- and selecting a column with smallest overhead in the AND plane of the set of equations representing the PLA, the first sub-PLA includes products in which said splitting variable is in complemented form, the second sub-PLA includes products in which said splitting variable is in uncomplemented form, said splitting variable corresponding to a specific input, output and product in a set of equations representing the PLA;
- dividing the set of equations representing the PLA into a first set of equations representing the first sub-PLA and a second set of equations representing the second sub-PLA based on the splitting variable;
- determining a topological circuit representation of the equations representing the first sub-PLA and the equations representing the second sub-PLA;
- applying gating logic to the topological circuit representation of the equations representing the first sub-PLA and the equations representing the second sub-PLA;
- and
- controlling power consumption in the topological circuit representation of the equations representing the first sub-PLA and the equations representing the second sub-PLA so only one of the topological circuit representation of the first sub-PLA and the second sub-PLA contributes to power consumption,
- wherein an OR plane of the topological circuit representation of the first sub-PLA is separated from an OR plane of the topological circuit representation of the second sub-PLA.
5 more elements
A program storage device readable by a machine comprising instructions that cause the machine to:
- determine an optimum splitting variable for dividing a programmable logic array (PLA) into a first sub-PLA and a second sub-PLA, said first sub-PLA and said second sub-PLA each having an AND plane and an OR plane by avoiding unbalanced columns in an AND plane of a set of equations representing the PLA;
- and selecting a column with smallest overhead in the AND plane of the set of equations representing the PLA, the first sub-PLA includes products in which said splitting variable is in complemented form, the second sub-PLA includes products in which said splitting variable is in uncomplemented form, said splitting variable corresponding to a specific input, output and product in a set of equations representing the PLA;
- divide the set of equations representing the PLA into a first set of equations representing the first sub-PLA and a second set of equations representing the second sub-PLA based on the splitting variable;
- determine a topological circuit representation of the first sub-PLA and the second sub-PLA;
- apply gating logic to the topological circuit representation of the first sub-PLA and the second sub-PLA;
- and
- control power consumption in the topological circuit representation of the first sub-PLA and the second sub-PLA so only one of the first sub-PLA and the second sub-PLA contributes to power consumption,
- wherein in the topological circuit representation an OR plane of the first sub-PLA is separated from an OR plane of the second sub-PLA.
5 more elements
Dependencies are inferred from the claim text.