Method for placing electrostatic discharge clamps within integrated circuit devices

A computer program product residing on a computer usable medium for placing a plurality of electrostatic discharge (ESD) protection devices within an integrated circuit design, said computer program product comprising:

• program code means for defining a region within said integrated circuit design;
• program code means for generating a list of ESD-susceptible circuits located within said defined region;
• program code means for determining a preferred location for placing an ESD protection device within said region;
• program code means for placing said ESD protection device at said determined preferred location;
• program code means for determining whether or not any ESD-susceptible circuit within said list of ESD-susceptible circuits is protected by the placement of said ESD protection device;
• and
• program code means for generating a set of all ESD-susceptible circuits within said integrated circuit design and associating said set of all ESD-susceptible circuits with said ESD protection device if all ESD-susceptible circuits within said list of ESD-susceptible circuits are protected by the placement of said ESD protection device.

A method for checking effectiveness of a plurality of electrostatic discharge (ESD) protection devices placed within an integrated circuit design, said method comprising:

• identifying all ESD-susceptible circuits within said integrated circuit design;
• modeling each of said plurality of ESD protection devices associated with said ESD-susceptible circuits as a voltage source connected in series with a resistor;
• modeling an ESD event striking on one of said ESD-susceptible circuits as a current source at said one of said ESD-susceptible circuits;
• comparing a voltage on said one of said ESD-susceptible circuits during said ESD event to a predetermined voltage threshold;
• and
• in a determination that said voltage on said one of said ESD-susceptible circuits during said ESD event exceeds said predetermined voltage threshold, designating said one of said ESD-susceptible circuits as failing an ESD check.

A computer program product residing on a computer usable medium for checking effectiveness of a plurality of electrostatic discharge (ESD) protection devices placed within an integrated circuit design, said computer program product comprising:

• program code means for identifying all ESD-susceptible circuits within said integrated circuit design;
• program code means for modeling each of said plurality of ESD protection devices associated with said ESD-susceptible circuits as a voltage source connected in series with a resistor;
• program code means for modeling an ESD event striking on one of said ESD-susceptible circuits as a current source at said one of said ESD-susceptible circuits;
• program code means for comparing a voltage on said one of said ESD-susceptible circuits during said ESD event to a predetermined voltage threshold;
• and
• in a determination that said voltage on said one of said ESD-susceptible circuits during said ESD event exceeds said predetermined voltage threshold, program code means for designating said one of said ESD-susceptible circuits as failing an ESD check.