Method and apparatus for generating and verifying libraries for ATPG tool

An apparatus for generating a design-for-test (DFT) library for automatic test pattern generation (ATPG), the ATPG generating test vectors for an integrated circuit (IC) design including cells, a source design library of the IC design including modules corresponding to the cells, said apparatus comprising:

• means for creating a synthesis library including primitives to be used to create the modules, the primitives being the same as primitives used by the ATPG tool;
• means for creating a register transfer level (RTL) description for each module;
• means for performing synthesis using the synthesis library and the RTL description of each module, so as to create a gate level description for each module;
• means for generating the DFT library, said means for generating the DFT library including means for converting a hardware description language (HDL) of the gate level description into a script language for the ATPG tool so as to create a DFT file for each module;
• and
• means for verifying the DFT library, said means for verifying comprising:
• means for converting the DFT files into a RTL description so as to create a pseudo-RTL description for each module;
• and
• means for comparing the RTL description and the pseudo-RTL description.

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for generating a design-for-test (DFT) library for an automatic test pattern generator (ATPG) tool, the ATPG tool generating test vectors for an integrated circuit (IC) design including cells, and a source design library of the IC design including modules corresponding to the cells, said method comprising:

• creating a synthesis library including primitives to be used to create the modules, the primitives being the same as primitives used by the ATPG tool;
• creating a register transfer level (RTL) description for each module;
• performing synthesis using the synthesis library and the RTL description of each module, so as to create a gate level description for each module;
• generating the DFT library by converting a hardware description language (HDL) of the gate level description into a script language for the ATPG tool so as to create a DFT file for each module;
• and
• verifying the DFT library, said verifying comprising:
• converting the DFT files into a RTL description so as to create a pseudo-RTL description for each module;
• and
• comparing the RTL description and the pseudo-RTL description.