Out-of-order calculation of error detection codes
AssigneeSiliquent Technologies Inc.
InventorAmit Oren
Life of this patent
Estimating the term…
Abstract
A method for error detection includes receiving a block of data that is divided into a plurality of sub-blocks having respective offsets within the block and processing the data in each of the sub-blocks so as to compute respective partial error detection codes for the sub-blocks. The partial error detection codes of the sub-blocks are modified responsive to the respective offsets, and the modified partial error detection codes are combined to determine a block error detection code for the block of data.
Claims8
A method for detecting an error in a block of data to which an error detection code has been appended, the block having been divided for transmission over a network into a sequence of sub-blocks, each of the sub-blocks at a respective offset within the block of data, the method comprising:
- receiving over the network a series of Transport Control Protocol/Internet Protocol (TCP/IP) data packets containing the sub-blocks in an order that does not necessarily correspond to the sequence;
- computing respective partial error detection codes for the sub-blocks in substantially the order in which the sub-blocks are received;
- combining the partial error detection codes of the sub-blocks to determine a total error detection code of the block;
- and
- comparing the total error detection code to the appended error detection code in order to detect the error.
A data receiver, for receiving a block of data to which an error detection code has been appended, the block having been divided for transmission over a network into a sequence of sub-blocks, each of the sub-blocks at a respective offset within the block of data, the receiver comprising:
- a sub-block receiving circuit, which is adapted to receive over the network a series of Transport Control Protocol/Internet Protocol (TCP/IP) data packets containing the sub-blocks in an order that does not necessarily correspond to the sequence and to extract the sub-blocks from the packets;
- and
- an error detection circuit, coupled to compute respective partial error detection codes for the sub-blocks in substantially the order in which the sub-blocks are received, to combine the partial error detection codes of the sub-blocks to determine a total error detection code of the block, and to compare the total error detection code to the appended error detection code in order to detect the error.
Dependencies are inferred from the claim text.