Systems and methods of partitioning data to facilitate error correction
AssigneeHewlett-Packard Development Company, L.P.
InventorsTheodore Carter Briggs, Jay Tsao
Life of this patent
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Abstract
Systems and methods are provided for detecting and correcting bit errors in data structures. A data block and/or data structure is partitioned into adjacent bit pair domains, such that a single adjacent bit pair from each memory device is assigned to a given adjacent bit pair domain. The bits in the adjacent bit pair domain are processed by an error correction unit sequentially or in parallel, and then recombined to be written into memory or transmitted to a requestor.
Claims24
A system for detecting and correcting errors in a data structure, comprising:
- a data structure stored in a plurality of memory devices associated with a memory address;
- a data separator that partitions the data structure into adjacent bit pair domains, such that a single adjacent bit pair from each of the plurality of memory devices is assigned to an adjacent bit pair domain;
- and
- an error detection and correction (EDC) component that detects and corrects errors associated with a given adjacent bit pair domain.
A memory system comprising:
- a plurality of memory devices operative to store a data structure over the plurality of memory devices corresponding to a given memory address;
- a buffer/multiplexer device that transmits and receives the data structures over a first bus and transmits and receives adjacent bit pair domain data over a second bus;
- the adjacent bit pair domain data comprising data bits and check bits assigned to a given adjacent bit pair domain, such that a single adjacent bit pair from each of the plurality of memory devices corresponding to the given memory address is assigned to a given adjacent bit pair domain for each of a plurality of adjacent bit pair domains;
- and
- a controller operative to transmit and receive adjacent bit pair domain data over the second bus and operative to transmit and receive data blocks corresponding to the adjacent bit pair domain data over a third bus.
An error correction system, comprising:
- means for partitioning a data structure into a plurality of adjacent bit pair domains, each adjacent bit pair domain being populated with a single adjacent bit pair from each of a plurality of memory devices associated with a given memory address;
- and
- means for detecting and correcting single bit errors and adjacent double bit errors associated with a respective adjacent bit pair domain.
A method of reading data from a plurality of memory device defining a system memory, the method comprising:
- reading a data structure from rows of the plurality of memory devices associated with a given memory address;
- separating the data structure into a plurality of adjacent bit pair domains, each adjacent bit pair domains having a single adjacent bit pair from each of the plurality of memory devices associated with the given memory address;
- and
- performing error detection and correction on the plurality of adjacent bit pair domains.
A method of storing data into a plurality of memory device defining a system memory, the method comprising:
- receiving a data block for storage;
- assigning adjacent data bit pairs to respective adjacent bit pair domains, each adjacent bit pair domain having a single adjacent bit pair associated with each of a plurality of memory devices for a given memory address;
- generating check bits for each adjacent bit pair domain;
- populating each respective adjacent bit pair domain with its associated check bits;
- combining the adjacent bit pair domains to provide a data structure for storage;
- and
- writing the data structure into the plurality of memory devices at the given memory address.
Dependencies are inferred from the claim text.