Adaptive runtime repairable entry register file
AssigneeInternational Business Machines Corporation
InventorDavid Arnold Luick
Life of this patent
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Abstract
Methods and apparatus are disclosed that provide for improved addressing of a register file in a computer system. The register file has one or more redundant words. A logical address in an instruction is mapped, during a predecode operation, to a physical address having a larger address space than the logical address. Addresses of nonfaulty words are mapped to the same word in the larger address space as the logical address. Logical addresses that point to faulty words are mapped to a redundant word that is in the larger address space but not in the address space of the logical address. Because all addresses presented to a register file decoder at access time point to nonfaulty words, no delay penalty associated with address compare during the access time is required.
Claims18
A method for using a redundant word in a register file in place of a faulty word in the register file comprising the following steps:
- fetching an original instruction from a first storage;
- mapping a logical address having a logical addressing space in the original instruction to a physical address having a physical addressing space, the physical addressing space being larger than the logical addressing space;
- if the logical address points to the faulty word in the register file, making the physical address the address of the redundant word, the redundant word being in the physical addressing space, but the redundant word not being in the logical addressing space;
- and
- if the logical address does not point to the faulty word in the register file, using the logical address as the physical address.
A computer system comprising:
- a register file having a number of words within an addressing space of a logical address, and a redundant word not addressable by the logical address;
- a predecode unit that maps the logical address to a physical address, the physical address having a larger address space than the logical address;
- a register addressing portion capable of accessing any word within the addressing space of the physical address, without use of an address compare;
- and
- a diagnostic unit capable of identifying a faulty word in the register file and controlling the predecode unit to map the logical address to a physical address responsive to the identity of the faulty word.
Dependencies are inferred from the claim text.