Implementation of test patterns in automated test equipment
AssigneeBroadcom Corporation
InventorHaluk Konuk
Life of this patent
Estimating the term…
Abstract
An improved automated testing system that decreases the number of test signals that must be stored in the tester pattern memory for a timed test pattern. In the present invention, a timed test pattern is controlled by a timing generator operable to change the timing interval of individual test cycles during the timed test pattern between first and second timing intervals, thereby decreasing the number of test signals stored in pattern memory for the timed test pattern. The method and apparatus of the present invention can be implemented to test integrated circuits comprising circuitry operating in first and second time domains wherein the first and second timing intervals of the timed test pattern correspond to the first and second time domains of the circuit, respectively.
Claims20
A testing apparatus, for testing the operation of an integrated circuit, comprising:
- pattern memory for storing test signals corresponding to individual test cycles within a timed test pattern;
- pin electronics connected to said integrated circuit, said pin electronics for transmitting a plurality of said test signals to said integrated circuit and receiving to a plurality of output signals from said integrated circuit in response to said test signals;
- digital compare circuitry for controlling said output signals to a predetermined reference output signal;
- and
- a timing generator for controlling the storing of said test signals during said timed test pattern;
- wherein said timing generator is for changing the timing interval of individual test cycles during said timed test pattern between first and second timing intervals, thereby decreasing the number of test signals stored in said pattern memory for said timed test pattern.
A method of testing an integrated circuit, comprising:
- generating a timed test pattern comprising a plurality of test signals;
- storing said test signals corresponding to individual test cycles of said timed test a pattern in pattern memory;
- transmitting said timed test pattern to said integrated circuit;
- receiving a plurality of output signals from said integrated circuit in response to said timed test pattern;
- comparing said output signals to a predetermined reference output signal;
- wherein said timed test pattern is controlled by a timing generator for changing change the timing interval of individual test cycles during said timed test pattern between first and second timing intervals, thereby decreasing the number of test signals stored in said pattern memory for said timed test pattern.
An integrated circuit, wherein during manufacturing of said integrated circuit, operational characteristics of said integrated circuit are tested by a testing apparatus, said testing apparatus comprising:
- pattern memory for storing test signals corresponding to individual test cycles within a timed test pattern;
- pin electronics connected to said integrated circuit, said pin electronics for transmitting transmit a plurality of said test signals to said integrated circuit and receiving a plurality of output signals from said integrated circuit in response to said test signals;
- digital compare circuitry for comparing said output signals to a predetermined reference output signal;
- and
- a timing generator for controlling storing the said test signals during said timed test pattern;
- wherein said timing generator for changing the timing interval of individual test cycles during said timed test pattern between first and second timing intervals, thereby decreasing the number of test signals stored in said pattern memory for said timed test pattern.
An integrated circuit, wherein during manufacturing of said integrated circuit, operational characteristics of said integrated circuit are tested by a method, comprising:
- generating a timed test pattern comprising a plurality of test signals;
- storing said test signals corresponding to individual test cycles of said timed test a pattern in pattern memory;
- transmitting said timed test pattern to said integrated circuit;
- receiving a plurality of output signals from said integrated circuit in response to said timed test pattern;
- comparing said output signals to a predetermined reference output signal;
- wherein said timed test pattern is controlled by a timing generator for changing the timing interval of individual test cycles during said timed test pattern between first and second timing intervals, thereby decreasing the number of test signals stored in said pattern memory for said timed test pattern.
Dependencies are inferred from the claim text.