Fault detecting method and layout method for semiconductor integrated circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsTakaki Yoshida, Reisuke Shimoda
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Abstract
The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor integrated circuit using a fault list corresponding to information on sites in the semiconductor integrated circuit where a fault is likely to occur or information required to reduce such faults. In addition, the fault detecting method and the layout method perform ordering of faults with their likelihood and weighting of the faults, taking into consideration physical information on a mask pattern within a chip or records of actual use of cells or functional blocks.
Claims6
A fault detecting method for a semiconductor integrated circuit comprising:
- providing a fault list comprising (a) information identifying physical sites on a physical layout of a semiconductor integrated circuit where a possible fault is likely to occur, and (b) information required to reduce faults;
- detecting faults in accordance with said fault list in a semiconductor integrated circuit to which said fault list corresponds;
- calculating a density of a mask pattern corresponding to mask information obtained from a layout device for laying out the semiconductor integrated circuit to which said fault list corresponds;
- calculating a likelihood of occurrence for each possible fault depending on the density of the mask pattern;
- weighting the arranged possible faults according to said calculated likelihoods of occurrence;
- arranging the possible faults in the fault list in order according to their likelihood of occurrence to create an ordered fault list;
- and
- detecting faults in said semiconductor integrated circuit by using the ordered fault list,
- wherein the fault list comprises data about a likelihood of a fault occurring at a physical site.
A fault detecting method for a semiconductor integrated circuit comprising:
- first detecting faults in a semiconductor integrated circuit to create a detection result;
- combining said detection result with (a) information about physical sites on a physical layout of the semiconductor integrated circuit to which said fault list corresponds where a possible fault is likely to occur and (b) information required to reduce faults, to create a fault list;
- again detecting faults according to said fault list in such semiconductor integrated circuit;
- calculating a density of a mask pattern corresponding to mask information obtained from a layout device for laying out the semiconductor integrated circuit to which said fault list corresponds;
- calculating a likelihood of occurrence for each possible fault depending on the density of the mask pattern;
- weighting the arranged possible faults according to said calculated likelihoods of occurrence;
- arranging the possible faults in order according to their likelihood of occurrence to create an ordered fault list;
- and
- second detecting possible faults in a semiconductor integrated circuit using the ordered fault list,
- wherein the fault list comprises data about a likelihood of a possible fault occurring at a physical site.
Dependencies are inferred from the claim text.