Simultaneous multiprocessor memory testing and initialization
AssigneeAdvanced Micro Devices, Inc.
InventorsWilliam A. Moyes, Michael V. Mattress
Life of this patent
Estimating the term…
Abstract
In a system having a plurality of processing nodes, wherein each of the plurality of processing nodes has an assigned portion of system memory such that the assigned portion of system memory of each of the plurality of processing nodes is accessible by the plurality of processing nodes, a technique is presented that allows each of the plurality of processing nodes to perform a memory initialization and test of the processing node's assigned portion of system memory. One of the processing nodes can cause the others of the processing nodes to perform the memory initialization and test process or each processing node can automatically perform the memory initialization and test process.
Claims18
A method comprising:
- causing a plurality of processing nodes to perform a memory initialization and test process, wherein each of the plurality of processing nodes performs the memory initialization and test process on a corresponding local memory, wherein the corresponding local memory forms at least a portion of a system memory and is accessible by the plurality of processing nodes;
- wherein each of the plurality of processing nodes comprises a processor, a memory controller, and a communication interface to at least one other of the plurality of processing nodes;
- wherein the causing the plurality of processing nodes to perform the memory initialization and test process comprises one of the plurality of processing nodes sending a broadcast start message to all of the plurality of processing nodes.
A computer system comprising:
- a plurality of processing nodes, each of the processing nodes comprising a processor, a memory controller, and a communication interface to at least one other of the plurality of processing nodes,
- wherein each of the plurality of processing nodes has an assigned portion of system memory, wherein the assigned portion of system memory of each of the plurality of processing nodes is local to the processing node and is accessible by the plurality of processing nodes;
- wherein one of the plurality of processing nodes is configured to cause others of the plurality of processing nodes to perform a memory initialization and test process of the assigned portion of system memory of the respective processing node;
- wherein to cause the plurality of processing nodes to perform the memory initialization and test process the one of the plurality of processing nodes is further configured to send a broadcast start message to all of the plurality of processing nodes.
A computer system comprising:
- a plurality of processing nodes, each of the processing nodes comprising a processor, a memory controller, and a communication interface to at least one other of the plurality of processing nodes,
- wherein each of the plurality of processing nodes has an assigned portion of system memory, wherein the assigned portion of system memory of each of the plurality of processing nodes is local to the processing node and is accessible by the plurality of processing nodes;
- wherein each of the plurality of processing nodes is configured to perform a memory initialization and test process of the assigned portion of system memory of the respective processing node;
- wherein to cause the plurality of processing nodes to perform the memory initialization and test process one of the plurality of processing nodes is further configured to send a broadcast start message to all of the plurality of processing nodes.
Dependencies are inferred from the claim text.