Circuits and methods for measuring signal propagation delays on integrated circuits

A method of measuring a signal propagation delay of a signal path defined between first and second synchronous memory elements on a programmable logic device, the method comprising:

• providing a clock signal to a circuit under test providing the signal path, the clock signal having a predetermined frequency;
• receiving the clock signal and a signal at an output of the signal path;
• dividing the clock signal by a predetermined dividing function to provide a divided clock signal;
• counting a number of pulses in the signal at the output of the signal path;
• counting a number of pulses in the divided clock signal;
• and
• comparing the number of pulses in the signal at the output of the signal path to the number of pulses in the divided clock signal to identify the signal propagation delay.

A test circuit for measuring the signal propagation delay through a signal path, the test circuit comprising:

• means for providing a clock signal to a circuit under test providing the signal path, the clock signal having a predetermined frequency;
• means for providing a data signal to the signal path;
• means for counting a number of pulses in the data signal at an output of the signal path;
• means for dividing the clock signal by a predetermined dividing function to provide a divided clock signal;
• means for counting a number of pulses in the divided clock signal;
• and
• means for comparing the number of pulses in the data signal to the number of pulses in the divided clock signal to measure the signal propagation delay.

A delay verification circuit, comprising:

• a first divider coupled to receive a data signal and a clock signal, the first divider being adapted to provide a first divided signal in response to rising edge transitions of the clock signal;
• a test circuit coupled to receive the first divided signal and adapted to propagate the first divided signal from an input to an output of the test circuit, wherein a delay is the time required to propagate the first divided signal from the input to the output of the test circuit;
• a second divider coupled to receive the clock signal and coupled to receive the first divided signal from the test circuit, the second divider being adapted to provide a second divided signal in response to rising edge transitions of the clock signal;
• a first counter coupled to receive the second divided signal and adapted to provide a first count, the first count being a number of rising edge transitions in the second divided signal during a test period;
• and
• a second counter coupled to receive a divided clock signal and adapted to provide a second count, the second count being a number of rising edge transitions in the divided clock signal during the test period, wherein the delay is verified if the first and second counts are equal.