Long path at-speed testing

An apparatus configured to generate an at-speed test path delay comprising:

• means for coupling a plurality of first base circuits to a plurality of second base circuits via a plurality of base circuit paths on a layout, wherein (i) each of said plurality of base circuit paths has a time delay, (ii) each of said plurality of first base circuits are positioned throughout the layout, and (iii) each of said plurality of second base circuits are positioned throughout the layout;
• means for disposing (i) a first test circuit in a first distal location outside of said layout and (ii) second test circuit in a second distal location outside of said layout;
• and
• means for coupling said first test circuit to said second test circuit to generate said test path delay from said first test circuit to said second test circuit incrementally longer than any of said time delays generated by any of said base circuit paths.

A method of generating an at-speed test path delay comprising the steps of:

• (A) coupling a plurality of first base circuits to a plurality of second base circuits via a plurality of base circuit paths on a layout, wherein (i) each of said plurality of base circuit paths has a time delay, (ii) each of said plurality of first base circuits are positioned throughout the layout, and (iii) each of said plurality of second base circuits are positioned throughout the layout;
• (B) disposing (i) a first test circuit in a first distal location outside of said layout and (ii) a second test circuit in a second distal location outside of said layout;
• and
• (C) coupling said first test circuit to said second test circuit via a test circuit path, wherein said test circuit path is configured to have a test path delay less than an incremental delay plus said base circuit path delay.