Flexible method for satisfying complex system error handling requirements via error promotion/demotion
AssigneeIntel Corporation
InventorNhon Quach
Life of this patent
Estimating the term…
Abstract
A signaling mechanism associated with errors in a processor are promoted or demoted based on a set of stored values.
Claims22
A method of handling errors occurring in a processor comprising:
- promoting or demoting a signaling mechanism associated with an error based on a set of stored values,
- wherein said promoting or demoting a signaling mechanism includes demotion of a second signaling mechanism to a first signaling mechanism.
A method of handing errors in a processor having a plurality of types of errors, each of which is assigned to a signaling mechanism comprising:
- storing a promotion or demotion value for at least one error;
- detecting an error;
- and
- promoting or demoting the signaling mechanism for said error based on said stored value,
- wherein said promoting or demoting a signaling mechanism includes demotion of a second signaling mechanism to a first signaling mechanism.
Error handling logic for a processor having a plurality of error types each of which is assigned to a signaling mechanism comprising:
- a register storing a promotion or a demotion value for at least one error;
- error detection logic;
- and
- error promotion and error demotion logic receiving inputs from said register and said error detection logic and producing an output to one of said signaling mechanisms.
A computer-readable memory having stored thereon a plurality of instructions for handling errors in a processor having a plurality of types or errors each of which is assigned to a signaling mechanism, causing a processor to:
- promote or demote a signaling mechanism associated with an error based on a set of stored values,
- including demotion of a second signaling mechanism to a first signaling mechanism.
A method, comprising:
- identifying a plurality of error types;
- associating a plurality of signaling mechanisms with the plurality of error types;
- storing a set of values corresponding to the plurality of error types with each stored value representing one of the plurality of error types;
- detecting an error;
- and
- signaling the detected error with one of the plurality of signaling mechanisms associated with the error type of the stored value corresponding to the detected error type,
- wherein the error type of the stored value represents a demotion with respect to the detected error type.
An apparatus, comprising:
- a plurality of signaling mechanisms respectively associated with a plurality of error types;
- a storage circuit adapted to store a set of values corresponding to the plurality of error types with each stored value representing one of the plurality of error types;
- and
- an error handling circuit adapted to detect an error and signal the detected error with one of the plurality of signaling mechanisms associated with the error type of the stored value corresponding to the detected error type,
- wherein the error type of the stored value represents a demotion with respect to the detected error type.
Dependencies are inferred from the claim text.