System and method for speeding up EJTAG block data transfers

A method for transferring a plurality of data words between a test probe and a target processor over a serial link, the method comprising:

• directing the target processor to configure a test data in port to test data out port (“TDI-to-TDO”) path to include a data register and a fastdata register;
• without reconfiguring said TDI-to-TDO path, shifting each of the plurality of data words accompanied by a SPrAcc bit into said data register and said fastdata register of said TDI-to-TDO path, respectively, said SPrAcc bit indicative of a request for completion of a pending processor access.

A computer-readable medium comprising a programmable device described in software, the programmable device including a test access port comprising:

• a Fastdata register that is selectably connectable to a data register to form at least a portion of a test-data-in-port to test-data-out-port path, said Fastdata register configured to operate such that a fastdata access completes when a processor access is pending and said processor access is to a predetermined area of memory.

A method for transferring a plurality of data words between a test probe and a target processor over a link, the method comprising:

• in response to a request from the target processor for a serial data transfer, including control information in said serial data transfer, said control information indicative of a request for completion of a processor access;
• and
• receiving second control information that confirms said processor access was pending and a target address associated with said processor access falls within a predetermined acceptable range of memory addresses.