US 7,065,666 B2Granted

Apparatus and method for generating a delayed clock signal

AssigneeMicron Technology, Inc.

InventorLeel S. Janzen

Life of this patent

Estimating the term…

Loading patent…

Abstract

An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.

Claims8

Dependent claims

A clock signal generator having an input at which an input clock signal is applied and having an output at which an output clock signal is provided, the clock signal generator comprising:

a synchronizing circuit having an input terminal at which the input clock signal is applied and having an output terminal at which a first clock signal is provided, the synchronizing circuit generating the first clock signal based on the input clock signal;
and
a plurality of delay circuits, each having an input coupled to the output terminal of the synchronizing circuit, and having an activation terminal at which a selection signal is applied and further having an output terminal at which a respective delayed output clock signal is provided, each of the plurality of delay circuits having a respective time delay and operable to generate the respective delayed output clock signal having the respective time delay relative to the first clock signal when activated by the selection signal, one of the plurality of delay circuits activated by the selection signal to provide the respective delayed output clock signal as the output clock signal of the clock signal generator.

Dependencies are inferred from the claim text.

Facts

Application: 10/713,587Filed 13 Nov 2003
Published: US 2005/0108590 A119 May 2005
Granted: 20 Jun 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 7/1066
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: output…
G06F 1/04
Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00: generating or distributing clock signals or signals derived directly therefrom
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…