Interlocked synchronous pipeline clock gating

An integrated circuit comprising:

• one or more pipelines, each pipeline having two or more stages;
• one or more triggering inputs on one or more of said stages, said triggering inputs receiving one or more stage triggering events;
• one or more of said stages passing only valid data in a downstream direction through one or more of said pipelines responsive to one or more of said stage triggering events;
• and
• one or more stall inputs on one or more of said stages, said stall inputs receiving one or more delayed stall signals, each delayed stall signal occurring a delay time later than a stall signal at one or more downstream stages, and said each delayed stall signal selectively stalling one or more of said stages that receive said each delayed stall signal.

A method of operating stages of a synchronous pipeline, said method comprising the steps of:

• a) checking a stall-out signal for a previously asserted stall condition;
• b) passing an incoming stall signal through a stall-in latch to a stall-out latch;
• c) passing incoming data through an upstream pipeline stage in an opposite direction of said incoming stall signal;
• d) checking an output of said stall-in latch for an asserted stall condition;
• e) passing said output of said stall-in latch through said stall-out latch as said stall-out signal;
• f) passing data from said upstream pipeline stage through a current pipeline stage in an opposite direction of said incoming stall signal;
• and
• g) returning to step (a).

A method of operating stages of a synchronous pipeline, said method comprising the steps of:

• a) checking an output pipeline stage for valid data and only when valid data is found in said output pipeline, passing an incoming stall signal through a stall-in latch to a stall-out latch;
• b) checking a stall-out signal from said stall-out latch for an upstream asserted stall condition;
• c) passing incoming valid data through an input pipeline stage in an opposite direction of said incoming stall signal;
• d) checking said input pipeline stage for valid data and only when valid data is found in said input pipeline, passing said output of said stall-in latch through said stall-out latch as said stall-out signal;
• e) checking an output of said stall-in latch for an asserted stall condition;
• f) passing valid data through said output pipeline stage in an opposite direction of said incoming stall signal;
• and
• g) returning to step (a).

An integrated circuit comprising:

• one or more pipelines, each pipeline having two or more stages;
• one or more triggering inputs on one or more of said stages, said triggering inputs receiving one or more stage triggering events;
• one or more of said stages passing only valid data in a downstream direction through one or more of said pipelines responsive to one or more of said stage triggering events;
• one or more stall inputs on one or more of said stages, said stall inputs receiving one or more delayed stall signals, each delayed stall signal occurring a delay time later than a stall signal at one or more downstream stages, and said each delayed stall signal selectively stalling one or more of said stages that receive said each delayed stall signal;
• and
• a logic circuit generating delayed stall signals and said delayed valid signals using a handshake protocol based on one or more stall signals and one or more valid signals such that said handshake interlocks the passing of valid data between two or more adjacent stages in said pipeline, wherein one of the stages passes data only when said data is valid and when said stage is not stalled, said stage stalling only if said stage stores valid data and there is a stall condition at said stage.

An integrated circuit comprising:

• one or more pipelines, each pipeline having two or more stages;
• one or more triggering inputs on one or more of said stages, said triggering inputs receiving one or more stage triggering events;
• one or more of said stages passing only valid data in a downstream direction through one or more of said pipelines responsive to one or more of said stage triggering events;
• and
• one or more stall inputs on one or more of said stages, said stall inputs receiving one or more delayed stall signals, each delayed stall signal occurring a delay time later than a stall signal at one or more downstream stages, and said each delayed stall signal selectively stalling one or more of said stages that receive said each delayed stall signal, wherein during a stall condition, one or more stages upstream of said stall condition continue unstalled and effective storage capacity of said pipeline is increased in one or more of said stalled stages.

An integrated circuit comprising:

• one or more pipelines, each pipeline having two or more stages;
• one or more triggering inputs on one or more of said stages, said triggering inputs receiving one or more stage triggering events;
• one or more of said stages passing only valid data in a downstream direction through one or more of said pipelines responsive to one or more of said stage triggering events;
• one or more stall inputs on one or more of said stages, said stall inputs receiving one or more delayed stall signals, each delayed stall signal occurring a delay time later than a stall signal at one or more downstream stages, and said each delayed stall signal selectively stalling one or more of said stages that receive said each delayed stall signal;
• a logic circuit generating delayed stall signals using a handshake protocol based on one or more stall signals such that said handshake interlocks the passing of data between two or more adjacent stages in said pipeline, providing a progressive, stage by stage, stalling of said pipeline, where one or more of the upstream stages is stalled said delay time later than the adjacent downstream stage.