Hardware loops and pipeline system using advanced generation of loop parameters

A method comprising:

• first calculating a first loop condition of a first hardware loop from a particular instance of a loop setup instruction using a first arithmetic logic unit in a first pipeline;
• pipe a loop condition from the first pipeline to a second pipeline;
• second calculating a second loop condition of said first hardware loop from a loop setup instruction piped from the first pipeline using a second arithmetic logic unit in the second pipeline;
• and
• using results of said first calculating and said second calculating for propagating said loop conditions in each of the first and second pipelines to hardware registers associated with calculating parameters of said first hardware loop;
• and
• beginning to calculate said parameters using said first hardware loop, based on said loop conditions, prior to said propagating of said loop conditions in each of the first and second pipelines to the hardware registers.

An apparatus comprising:

• a first pipeline including a first arithmetic logic unit and a second pipeline including a second arithmetic logic unit, and
• a control unit coupled to the pipelines, the control unit adapted to:
• obtain loop setup instructions for a first hardware loop from a computer program, the loop setup instructions associated with a particular instance of execution of the first hardware loop;
• pipe a loop setup instruction from the first pipeline to the second arithmetic unit in the second pipeline;
• first calculate a first loop condition of said particular instance of execution of the first hardware loop from one of said loop setup instructions using the first arithmetic logic unit in the first pipeline;
• and
• second calculate a second loop condition of said particular instance of execution of the first hardware loop from the piped loop setup instruction using the second arithmetic logic unit in the second pipeline, in parallel with said first calculate.

An apparatus comprising a set of registers, a first pipeline, and a second pipeline;

• and
• a control unit coupled to the set of registers, the first pipeline and the second pipeline, the control unit adapted to:
• first propagate at least one loop condition of a particular instance of execution of a first hardware loop to the set of registers via the first pipeline;
• pipe at least one loop of the particular instance of execution of said first hardware loop to the second pipeline;
• second propagate at least one piped loop condition of the particular instance of execution of said first hardware loop to the set of registers via the second pipeline;
• and
• begin calculating data using said first hardware loop, prior to propagating the at least one loop condition of a particular instance of execution of said first hardware loop in the first pipeline to the set of registers and prior to propagating the at least one loop condition of the particular instance of execution of said first hardware loop in the second pipeline to the set of registers.

A system comprising:

• a static random access memory device;
• a processor coupled to the static random access memory device, wherein the processor includes a first set of registers, a first pipeline, a second pipeline, and a control unit adapted to:
• pipe a loop setup instruction from the first pipeline to a second arithmetic unit in the second pipeline;
• first calculate a first loop condition of a particular instance of execution of a first hardware loop from the loop setup instruction using a first arithmetic logic unit in the first pipeline;
• second calculate a second loop condition of said particular instance of execution of the first hardware loop from the loop setup instruction using the second arithmetic logic unit in the second pipeline, in parallel with the first calculate;
• and
• write the first and second loop conditions of said particular instance of execution of the first hardware loop to the first set of registers.

A system comprising:

• a static random access memory device;
• a processor coupled to the static random access memory device, wherein the processor includes a first set of registers, a second set of registers, a first pipeline, a second pipeline, and a control unit adapted to:
• write loop conditions of a first hardware loop to the first set of registers;
• propagate at least one of the loop conditions of said first hardware loop to the second set of registers via the first pipeline;
• pipe at least one of the loop conditions of said first hardware loop to the second pipeline;
• propagate at least one of the piped loop conditions of said first hardware loop to the second set of registers via the second pipeline;
• and
• begin calculating data using said first hardware loop prior to propagation of the at least one of the loop conditions of said first hardware loop in the first pipeline to the second set of registers and prior to propagation of the at least one of the loop conditions of said first hardware loop in the second pipeline to the second set of registers.