Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processor

A method for handling a plurality of instructions in a multi-stranded microprocessor pipeline, comprising:

• step for providing a condition code architectural register file for each strand and a condition code working register file;
• step for determining whether there is a condition code modifying instruction in the plurality of instructions;
• and
• if there is a condition code modifying instruction:
• step for assigning condition code architectural register file identification information to the condition code modifying instruction,
• step for assigning condition code working register file identification information to the condition code modifying instruction,
• step for providing register type information and strand identification information,
• step for indexing a storage location with the condition code architectural register file identification information and the strand identification information,
• step for storing the condition code working register file identification information in the location,
• step for executing the condition code modifying instruction, and
• step for storing a result of the executing in the condition code working register file dependent on the condition code working register file identification information and register type information.

A multi-stranded microprocessor, comprising:

• an instruction decode unit arranged to decode a plurality of instructions;
• an execution unit having a condition code architectural register file for each strand and a condition code working register file, wherein, if the instruction decode unit determines that there is a condition code modifying instruction in the plurality of instructions, the instruction decode unit is further arranged to assign condition code architectural register file identification information, condition code working register file identification information, register type information, and strand identification information to the condition code modifying instruction;
• and
• a rename and issue unit operatively connected to the instruction decode unit and the execution unit, wherein the rename and issue unit is arranged to store the condition code working register file identification information in a storage location indexed by the condition code architectural register file identification information and strand identification information,
• wherein the execution unit is arranged to execute the condition code modifying instruction and store a result of the execution in the condition code working register file, and wherein the result is copied to the appropriate condition code architectural register file dependent upon a status of the execution.