Back to results
US 7,065,633 B1Granted
System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
AssigneeATI International SRL
InventorsJohn S. Yates, Jr., Matthew F. Storch, Sandeep Nijhawan, Dale R. Jurich, Korbin S. Van Dyke
Life of this patent
Estimating the term…
Abstract
A computer concurrently executes a first operating system coded in a RISC instruction set and a second operating system coded in a CISC instruction set. When an exception is raised while executing a program coded in the RISC instruction set, an execution thread may be initiated under the CISC operating system. The exception may be delivered to the initiated thread for handling by the CISC operating system.
Claims44
A method, comprising the steps of:
- concurrently executing on a single computer a first operating system coded in a RISC instruction set, being an instruction set having a fixed-length instruction format and a load/store/operate organization, and a second operating system coded in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects, the CISC operating system being unmodified for execution on the computer of the RISC instruction set;
- and
- accepting an exception raised while executing a program coded in the RISC instruction set, and in response, initiating execution of a thread under the CISC operating system;
- delivering the exception to the initiated thread for handling by the CISC operating system.
1 more element
A method, comprising the steps of:
- concurrently executing on a single computer a first operating system coded in a RISC instruction set, being an instruction set having a fixed-length instruction format and a load/store/operate organization, and a second operating system coded in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects, the CISC operating system being unmodified for execution on the computer of the RISC instruction set;
- and
- accepting an exception occurring during execution of a program coded in the RISC instruction set, and routing the exception for handling in the CISC operating system.
A computer, comprising:
- a first operating system loaded into memory, being coded in a RISC instruction set, being an instruction set having a fixed-length instruction format and a load/store/operate organization;
- and
- a second operating system loaded into memory, being coded in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects, the CISC operating system being unmodified for execution on the computer of the RISC instruction set;
- and
- hardware and/or software designed to accept an exception occurring during execution of a program coded in the RISC instruction set, and to route the exception for handling in the CISC operating system.
2 more elements
A method, comprising the steps of:
- in response to an exception raised while executing a thread of a program coded in instructions of a first instruction set architecture, delivering the exception to an execution thread for execution of a handler for the exception, the handler's thread being distinct from the thread in which the program was executing, the handler's thread being an execution thread under an operating system coded in instructions of a second instruction set architecture, the handler being a handler of the operating system.
A computer, comprising:
- hardware and/or software designed to respond an exception raised while executing a thread of a program coded in instructions of a first instruction set architecture of the computer by delivering the exception to an execution thread for execution of a handler for the exception, the handler's thread being distinct from the thread in which the program was executing, the handler's thread being an execution thread under an operating system coded in instructions of a second instruction set architecture and running on the computer, the handler being a handler of the operating system.
Dependencies are inferred from the claim text.