Increasing memory access efficiency for packet applications
AssigneeIntel Corporation
InventorsJuan-Carlos Calderon, Jing Ling, Jean-Michel Caia, Vivek Joshi, Anguo T. Huang
Life of this patent
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Abstract
Memory access efficiency for packet applications may be improved by transferring full partitions of data. The number of full partitions written to external memory may be increased by temporarily storing packets using on-chip memory that is on a chip with the processor. Before writing packets to external memory, packets of length smaller than the external memory partition size may be temporarily stored in the on-chip memory until an amount corresponding to a full or nearly full partition has been collected, at which point the data can be efficiently written to an external memory partition.
Claims30
A memory access method for a packet-switching application, the method comprising:
- receiving a series of packets at a processor having on-chip memory formed on a chip with the processor,
- storing multiple packets in the on-chip memory, the multiple packets including one or more packets in a sequence of packets from the series of packets, and
- writing the stored packets to a partition in external memory in response to a combined size of stored packets equaling a predetermined amount.
An apparatus for a packet-switching application, the apparatus including:
- a processor;
- on-chip memory formed on a chip with the processor;
- and
- external memory comprising a second chip connected to the processor;
- wherein the processor comprises one or more components to:
- receive a series of packets,
- store multiple packets in the on-chip memory, the multiple packets including one or more packets in a sequence of packets from the series of packets, and
- write the stored packets to a partition in the external memory in response to a combined size of stored packets equaling a predetermined amount.
A computer readable medium or propagated signal having embodied thereon a computer program configured to cause a processor to implement a packet-switching application, the computer program comprising:
- a code segment configured to cause a processor to receive a series of packets,
- a code segment configured to cause a processor to store multiple packets in the on-chip memory, the multiple packets including one or more packets in a sequence of packets from the series of packets, and
- a code segment configured to cause a processor to write the stored packets to a partition in external memory in response to a combined size of stored packets equaling a predetermined amount.
A system for a packet-switching application, the system comprising:
- a processor having on-chip memory formed on a chip with the processor and external memory comprising a second chip connected to the processor;
- a port coupled to a transmission channel;
- and
- a link between the processor and the port,
- wherein the processor comprises one or more components to:
- receive a series of packets from the port,
- store multiple packets in the on-chip memory, the multiple packets including one or more packets in a sequence of packets from the series of packets, and
- writing the stored packets to a partition in external memory in response to a combined size of stored packets equaling a predetermined amount.
Dependencies are inferred from the claim text.