US 7,065,614 B1 · System and method for maintaining memory coherency within a multi-processor data processing system

Abstract

The current invention provides a system and method for maintaining memory coherency within a multiprocessor environment that includes multiple requesters such as instruction processors coupled to a shared main memory. Within the system of the current invention, data may be provided from the shared memory to a requester for update purposes before all other read-only copies of this data stored elsewhere within the system have been invalidated. To ensure that this acceleration mechanism does not result in memory incoherency, an instruction is provided for inclusion within the instruction set of the processor. Execution of this instruction causes the executing processor to discontinue execution until all outstanding invalidation activities have completed for any data that has been retrieved and updated by the processor.

Claims17

Dependent claims

For use in a data processing system having a memory coupled to multiple requesters, a memory coherency system, comprising:

a memory circuit coupled to provide a copy of requested data from the memory to a first requester, and to initiate invalidation operations to invalidate all read-only copies of the requested data that are stored by one or more other requesters, wherein the data is provided before the invalidation operations are completed;
and
a circuit included within the first requester and responsively coupled to the memory circuit to execute an instruction that causes the first requester to temporarily enter a stalled state until all of the invalidation operations have been completed.

Dependencies are inferred from the claim text.

System and method for maintaining memory coherency within a multi-processor data processing system

Life of this patent

System and method for maintaining memory coherency within a multi-processor data processing system

Life of this patent

Abstract

Claims17