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US 7,065,613 B1Granted
Method for reducing access to main memory using a stack cache
AssigneeMaxtor Corporation
InventorsLance Flake, Andrew Vogan
Life of this patent
Estimating the term…
Abstract
The invention is directed to efficient stack cache logic, which reduces the number of accesses to main memory. More specifically, in one embodiment, the invention prevents writing old line data to main memory when the old line data represents a currently unused area of the cache. In another embodiment, the invention prevents reading previous line data for a new tag from main memory when the new tag represents a currently unused area of the cache.
Claims20
A method comprising the steps of:
- providing a processor;
- providing a main memory associated with the processor;
- providing a stack cache associated with the processor, the stack cache including a stack pointer associated with a stack and a stack limit register, the stack cache further including a plurality of candidate lines each having a dirty flag, a valid flag, an address tag and a plurality of data bytes;
- determining whether to access the main memory based upon whether the access was or will be to an unused portion of the stack.
1 more element
A method comprising the steps of:
- providing a processor;
- providing a main memory associated with the processor;
- providing a stack cache associated with the processor, the stack cache including a stack having a stack pointer with a stack pointer value and a stack limit register having a stack limit value, the stack cache further including a plurality of candidate lines each having a dirty flag, a valid flag, an address tag and a plurality of data bytes;
- choosing a replacement line upon detection of a cache miss;
- and,
- writing the plurality of data bytes to the main memory, if the dirty flag of the chosen candidate line indicates that a change to one or more of the plurality of data bytes has occurred and the address tag value of the candidate line is not in an unused portion of the stack.
3 more elements
A method comprising the steps of:
- providing a processor;
- providing a main memory associated with the processor;
- providing a stack cache associated with the processor, the stack cache including a stack having a stack pointer with a stack pointer value, the stack cache further including a plurality of candidate lines each having an address tag and a plurality of data bytes;
- and,
- determining whether to write or read data between the cache and the main memory by comparing the stack pointer value with an address tag value.
2 more elements
Dependencies are inferred from the claim text.