Processor having cache structure and cache management method for elevating operation speed

A method of managing cache memory of a processor, the method comprising the steps of:

• (a) dividing the cache memory into a cache memory for normal programs and a cache memory for exception programs;
• (b) storing instructions and/or data for running the normal programs in the cache memory for normal programs and instructions and/or data for running the exception programs in the cache memory for exception programs;
• and
• (c) determining whether a currently running program is a normal program or an exception program, fetching instructions and/or data from either the cache memory for normal programs or the cache memory for exception programs according to a result of the determination, and inputting the fetched instructions and/or data to an instruction register;
• wherein the exception programs further comprise a predetermined subroutine for normal programs.

A method of managing cache memory of a processor, the method comprising the steps of:

• (a) dividing the cache memory into a first cache memory for normal programs and a second cache memory for exception programs, wherein the first cache memory and the second cache memory are physically separate;
• (b) determining whether a currently running program is a normal program or an exception program;
• (c) performing a cache lookup operation to find desired instructions and/or data;
• and
• (d) if a cache miss occurs as a result of step (c), searching for the desired instructions and/or data from a lower level of memory and, once found, storing the desired instructions and/or data in either the first cache memory for normal programs or the second cache memory for exception programs according to a result of step (b);
• wherein the exception programs comprise an interrupt process routine, an exception process routine and a reset process routine;
• wherein the exception programs further comprise a predetermined subroutine for normal programs.