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US 7,065,607 B2Granted
System and method for implementing a counter
AssigneeMicrosoft Corporation
InventorsPaul England, Marcus Peinado
Life of this patent
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AssigneeMicrosoft Corporation
InventorsPaul England, Marcus Peinado
Estimating the term…
A counter is provided which can be implemented in flash memory allowing longer life through fewer erasures. The counter is incremented using a method that minimizes bit transitions from 1 to 0. In one embodiment, the counter is implemented in m+n bits. The bits of the counter are grouped into a binary portion of the counter of m bits and a unary portion of the counter of n bits. In order to increment the counter, the unary portion of the counter is incremented first. When the unary portion of the counter reaches a specific value, the binary portion of the counter is incremented. This limits 1 to 0 bit transitions and allows a large range of unique values to be read from the counter. In another embodiment, two unary counters are formed, which dynamically change in size as the counter is incremented.
A method of implementing a counter, where the bits of said counter are dynamically divided into subsets, comprising a first subset of bits storing a first value and a second subset of bits storing a second value, and where an increment method minimizes bit transitions from one to zero, said method comprising:
A computer device for implementing a counter, where an increment method minimizes bit transitions from one to zero, said device comprising:
A computer-readable medium comprising computer-executable modules having computer-executable instructions for implementing a counter, where said counter comprises bits dynamically divided into subsets, comprising a first subset of bits storing a first value and a second subset of bits storing a second value, and where an increment method minimizes bit transitions from one to zero, said modules comprising:
Dependencies are inferred from the claim text.