Controller architecture for memory mapping

An apparatus for mapping a customer memory onto a plurality of physical memories, comprising:

• means for dividing a data width of input of a customer memory into k input blocks, where said k is an integer;
• means for converting said k input blocks into m input blocks, where said m is an integer;
• and
• means for combining said m input blocks into input to a plurality of physical memories, each of said plurality of physical memories having a data width of m blocks,
• wherein said m is greater than said k but less than twice said k.

A computer-readable medium having computer-executable instructions for performing a method for mapping a customer memory onto a plurality of physical memories, said method comprising:

• dividing a data width of input of a customer memory into k input blocks, where said k is an integer;
• converting said k input blocks into m input blocks, where said m is an integer;
• and
• combining said m input blocks into input to a plurality of physical memories, each of said plurality of physical memories having a data width of m blocks,
• wherein said m is greater than said k but less than twice said k.

An apparatus for mapping a customer memory onto physical memories, comprising:

• a first physical memory and a second physical memory onto which a customer memory may be mapped, said first physical memory and said second physical memory each having a data width of m blocks, said customer memory having a data width of k blocks, and said k and said m being integers;
• an address controller, communicatively coupled to said first physical memory and said second physical memory, for receiving first address information A of said customer memory, for outputting second address information A1 to said first physical memory, for outputting third address information A2 to said second physical memory, and for outputting index information index;
• a data input controller, communicatively coupled to said address controller, said first physical memory and said second physical memory, for receiving data DI of said customer memory, and said index information index, and for outputting data DI1 to said first physical memory and DI2 to said second physical memory, said DI1 and said DI2 having a data width of m blocks;
• and
• a data output controller, communicatively coupled to said first physical memory, said second physical memory, and said address controller though a delay unit, for receiving said index information index, for receiving output, with a width of said m blocks, of said first physical memory and said second physical memory, and for outputting said customer memory with a width of said k blocks,
• wherein said m is greater than said k but less than twice said k.

An apparatus for mapping a customer memory onto a plurality of physical memories, comprising:

• a plurality of physical memories onto which a customer memory may be mapped, each of said plurality of physical memories having a data width of m blocks, said customer memory having a data width of k blocks, and said k and said m being integers;
• an address controller, communicatively coupled to said plurality of physical memories, for receiving first address information of said customer memory, for outputting second address information to said plurality of physical memories, and for outputting index information;
• a data input controller, communicatively coupled to said address controller and said plurality of physical memories, for receiving data of said customer memory and said index information, and for outputting data with a data width of m blocks to said plurality of physical memories;
• and a data output controller, communicatively coupled to said plurality of physical memories and said address controller though a delay unit, for receiving said index information, for receiving output, with a width of said m blocks, of said plurality of physical memories, and for outputting said customer memory with a width of said k blocks,
• wherein said m is greater than said k but less than twice said k.