Interface for prototyping integrated systems
AssigneeSTMicroelectronics S.r.l.
InventorsStuart Ryan, Andrew Jones
Life of this patent
Estimating the term…
Abstract
An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the chip side port. The interface is constructed so that interrupt signals from an off-chip circuit can be conveyed on-chip in a manner such that the interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to an on-chip communication path. The same principle is applicable to power-down signals.
Claims14
An interface for carrying packets each comprising a plurality of fields between an on-chip communication path connected to at least one on-chip module and off-chip circuitry, said interface comprising;
- at least one chip-side port comprising a plurality of pins for conveying the fields of the packet in parallel;
- first and second circuit-side ports, each circuit-side port comprising a set of pins having a lower number than pins of said at least one chip-side port, each of said first and second circuit-side ports providing a unidirectional pathway between said interface and said off-chip circuitry;
- means for transmitting interrupt signals from said off-chip circuit to said on-chip communication path in a manner such that said interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to said on-chip communication path;
- and
- means for conveying power down signals between said off-chip circuit and said on-chip communication path in a manner indistinguishable from power down signals provided between on-chip modules connected to said on-chip communication path.
An interface for carrying packets each comprising a plurality of fields including a data field between an on-chip communication path connected to at least one on-chip module and off-chip circuitry, said interface comprising:
- at least one chip-side port comprising a plurality of pins for conveying the fields of the packet in parallel;
- first and second circuit-side ports each port comprising a set of pins having a lower number than the pins of said at least one chip-side port, each of said first and second circuit-side ports providing a unidirectional pathway for data between said interface and said off-chip circuitry;
- a set of interrupt connections for transmitting interrupt signals from said off-chip circuit to said on-chip communication path in a manner such that said interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to said on-chip communication path;
- and
- a set of power down connections for conveying power down signals between said off-chip circuit and said on-chip communication path in a manner indistinguishable from power down signals provided between on-chip modules connected to said on-chin communication path.
Dependencies are inferred from the claim text.