Method of providing an interface to a plurality of peripheral devices using bus adapter chips

A method of electrically coupling a plurality of interface modules to a CPU such that at least one of the interface modules can be disconnected without powering down the remaining interface modules or the CPU, said method comprising:

• mounting a CPU on a chassis;
• removably mounting a plurality of interface modules to said chassis;
• mounting a backplane printed circuit board on the chassis, wherein the backplane printed circuit board comprises at least one bus adapter chip for each of the plurality of interface modules, and wherein each bus adapter chip has a primary side and a secondary side, and wherein each bus adapter chip has electrical hardware that isolates the primary side from the secondary side when the corresponding interface module has been removed from the chassis;
• routing an I/O bus on said backplane printed circuit board from the primary side of the at least one bus adapter chip to the CPU;
• and
• routing an I/O bus on said backplane printed circuit board from the secondary side of the at least one bus adapter chip to the corresponding one of the interface modules.

A method of electrically coupling a plurality of interface modules to a CPU such that at least one of the interface modules can be removed without powering down the remaining interface modules or the CPU, said method comprising:

• mounting a backplane printed circuit board on the back of a chassis;
• connecting a CPU module to said backplane printed circuit board when mounting a CPU module on said chassis;
• and
• removably mounting a plurality of interface modules to the backplane printed circuit board;
• and
• connecting the plurality of interface modules to the backplane printed circuit board with bus adapter chips configured to provide electrical termination and isolation between the interface modules and the CPU module when a interface module is removed.

A system for electrically coupling a central processing unit (CPU) of a server to a plurality of interface modules, the system comprising:

• first means routing an I/O bus having a first format from said central processing unit to primary sides of a plurality of bus adapter chips;
• and
• second means for routing an I/O bus of said first format from secondary sides of said bus adapter chips to respective ones of said interface modules,
• wherein the first means comprise means for electrically isolating the central processing unit from electrical disruption when one of the interface modules is removed.