Precision jitter-free frequency synthesis

A method of synthesizing one or more clock signals of a selected frequency, comprising the steps of:

• for the selected frequency, determining a frequency select integer word and a frequency divide integer;
• generating a plurality of clock phases from a phase-locked loop, the phase-locked loop including a frequency divider for dividing a clock signal by the frequency divide integer so that the plurality of clock phases are at a frequency determined by the frequency divide integer;
• adding at least a portion of the frequency select integer word to an accumulated integer to generate a first select value;
• selecting a first one of the plurality of clock phases according to the first select value;
• adding at least a portion of the frequency select integer to an accumulated integer to generate a second select value;
• selecting a second one of the plurality of clock phases according to the second select value;
• and
• generating the output clock signal from the first and second selected ones of the plurality of clock phases.

An electronic system, comprising:

• system functions, coupled to receive a system clock signal at a desired frequency;
• a reference clock circuit, for generating a reference clock;
• a control circuit;
• and
• a clock generator circuit, comprising:
• a phase-locked loop for generating a plurality of clock phases, the phase-locked loop comprising:
• a voltage controlled oscillator, for generating a plurality of clock phases at a frequency controlled by a control input to the voltage controlled oscillator;
• circuitry for generating the control input to the voltage controlled oscillator responsive to phase differences between a reference clock signal based on the reference clock, and a feedback clock signal;
• and
• a feedback frequency divider, for generating the feedback clock signal from one of the clock phases generated by the voltage controlled oscillator, divided by a feedback integer value applied by the control circuit;
• and
• a frequency synthesis circuit for generating the system clock signal from the plurality of clock phases, responsive to a frequency select integer word applied by the control circuit.
• wherein the frequency circuit comprises:
• a first multiplexer, for forwarding a selected one of the plurality of clock phases responsive to a first select signal;
• a second multiplexer, for forwarding a selected one of the plurality of clock phases responsive to a second select signal;
• a first adder leg, having an input for receiving at least a portion of the frequency select integer word, for generating the first select signal corresponding to a sum of the received portion of the frequency selectinteger word and a accumulated value.

A method of constructing a frequency synthesis circuit, comprising the steps of:

• selecting a range of digital frequency integers;
• selecting a first upper limit and a lower limit for a feedback divide integer;
• generating a plurality of ratios of feedback divide integer to digital frequency integer, the plurality of ratios including each possible ratio of the range of digital frequency integers and a range of feedback divide integers defined by the first upper limit and the lower limit;
• ordering the plurality of ratios by value;
• for each of adjacent ordered ratios, determining a maximum frequency error point and a maximum frequency error value;
• analyzing the results of the determining steps;
• repeating the generating, ordering, determining, and analyzing step for a plurality of upper limits;
• responsive to the repeated analyzing steps, selecting one of the plurality of upper limits;
• and
• manufacturing a frequency synthesis circuit including a phase-locked loop for generating a plurality of clock phases, the phase-locked loop comprising:
• a voltage controlled oscillator, for generating a plurality of clock phases at a frequency controlled by a control input to the voltage controlled oscillator;
• circuitry for generating the control input to the voltage controlled oscillator responsive to phase differences between a reference clock signal and a feedback clock signal;
• and
• a feedback frequency divider, for generating the feedback clock signal from one of the clock phases generated by the voltage controlled oscillator, divided by a feedback integer value that ranges from the lower limit to the selected one of the plurality of upper limits.