Encoded clocks to distribute multiple clock signals to multiple devices in a computer system
AssigneeSun Microsystems, Inc.
InventorDrew G. Doblar
Life of this patent
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Abstract
An apparatus and method for distributing multiple clock signals to multiple devices using an encoded clock signal is provided. A source clock signal can be encoded to result in an encoded system clock. The encoded system clock can be distributed to multiple devices in a computer system. The devices can decode the encoded system clock signal to generate a system clock signal and a global clock signal. The system clock signal and the global clock signal can then be distributed to their respective clock loads on each device. In certain embodiments, additional information, such as state information, can be encoded into the encoded system clock. A device can be configured to decode the additional information and can alter its state accordingly.
Claims27
An apparatus comprising:
- a clock encoding circuit configured to receive a source clock signal, wherein the clock encoding circuit is configured to generate an encoded system clock signal using the source clock signal;
- a clock decoding circuit including a phase locked loop (PLL), wherein the clock decoding circuit is configured to receive the encoded system clock signal at a first input of the PLL, wherein the clock decoding circuit is configured to generate a phase signal and a core clock signal using the encoded source clock signal;
- and
- a clock generating circuit configured to generate a global clock signal using the phase signal and the core clock signal, and wherein the clock generating circuit is configured to generate a system clock signal that is synchronous with the global clock signal using the encoded clock signal.
A computer system comprising:
- a clock encoding circuit configured to receive a source clock signal, and wherein the clock encoding circuit is configured to generate an encoded clock signal using the source clock signal;
- and
- a plurality of devices coupled to the clock encoding circuit, wherein each of the plurality of devices includes:
- a clock decoding circuit including a phase locked loop (PLL), wherein the clock decoding circuit is configured to receive the encoded system clock signal at a first input of the PLL, wherein the clock decoding circuit is configured to generate a phase signal and a core clock signal using the encoded source clock signal, and
- a clock generating circuit configured to generate a global clock signal using the phase signal and the core clock signal, and wherein the clock generating circuit is configured to generate a system clock signal that is synchronous with the global clock signal using the encoded clock signal.
Dependencies are inferred from the claim text.