Detection of added or missing forwarding data clock signals
AssigneeHewlett-Packard Development Company, L.P.
InventorDavid W. Hartwell
Life of this patent
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Abstract
A system is disclosed that detects data forwarding clock errors including both missing and additional clock signals. The system provides for a phase locked loop (PLL) that locks onto a data forwarding source synchronous clock signal wherein the PLL outputs a system clock whose frequency is the average of the data forwarding clock frequency. The data forwarding clock signals and the system clock signals are counted separately and when a discrepancy occurs the receiving system is informed that an error has occurred. The receiving system will handle the error in its routine fashion. The counters and the PLL are synchronized to be sure that the PLL has acquired a lock before the error detection is enabled.
Claims16
An error detection system for a clock signal comprising:
- a first counter that receives and counts the clock signal,
- a phase-locked loop circuit that receives the clock signal and outputs a second clock signal,
- a second counter that receives and counts the second clock signal,
- a comparator that receives and compares the outputs of the first and the second counters, and
- an error output from the comparator that is true when the counts of the first and second counters are unequal.
A method for detecting clock signal errors comprising the steps of:
- a first counting of the first clock signals,
- providing a second clock signal with a frequency that is locked to the average frequency of the first clock signal,
- a second counting of the second clock signals,
- detecting a difference between the first and the second countings, and
- signaling an error therewith.
A system for detecting errors in a first clock signal, the system comprising:
- means for counting the first clock signal,
- means, responsive to the first clock signal, for generating a second clock signal,
- means for counting the second clock signal,
- means for comparing the count of the first clock signal with the count of the second clock signal, and
- means for generating an error when the count of the first clock signal differs from the count of the second clock signal.
Dependencies are inferred from the claim text.