Jitter reduction

A digital circuitry, operative repetitively to perform a series of processing cycles, comprising:

• a plurality of individual circuit units, each circuit unit comprising:
• an input signal processing circuit performing, in each cycle, a predetermined processing operation on one or more input signal(s) received by the digital circuitry to derive therefrom one or more first signal(s), said predetermined processing operation being commenced in response to a first clock signal,
• a first clocked element receiving said one or more first signal(s) and a second clock signal, and producing one or more second signal(s), said first docked element being switchable by said second clock signal between a first responsive state, in which the first clocked element changes said one or mote second signal(s) in response to a change in said one or more first signal(s), and a first non-responsive state in which no change in said one or more second signal(s) occurs,
• a second clocked element receiving said one or more second signal(s) and a third clock signal, and producing one or more output signal(s) of said digital circuitry, said second clocked element being switchable by said third clock signal between a second responsive state, in which the second clocked element changes said one or more output signal(s) in response to a change in said one or more second signal(s), and a second non-responsive state in which no change in said one or more output signal(s) occur, and
• a clock generating circuitry generating the second and third clock signals from the first clock signal, the second clock signal being delayed relative to the first clock signal by a preselected delay time and said third clock signal being delayed relative to the first clock signal by less than said preselected delay time such that in each cycle the first clocked element enters said first non-responsive state before the end of said predetermined processing operation, and said second clocked element enters said second responsive state when the first clocked element is in said first non-responsive state.

A mixed-signal circuitry, including:

• a digital circuitry, operative repetitively to perform a series of processing cycles, comprising:
• an input signal processing circuit performing, in each cycle, a predetermined processing operation on one or more input signal(s) received by the digital circuitry to derive therefrom one or more first signal(s), said predetermined processing operation being commenced in response to a first clock signal,
• a first clocked element receiving said one or more first signal(s) and a second clock signal, and producing one or more second signal(s), said first clocked element being switchable by said second dock signal between a first responsive state, in which the first clocked element changes said one or more second signal(s) in response to a change in said one or more first signal(s), end a first non-responsive state in which no change in said one or more second signal(s) occurs,
• a second clocked element receiving said one or more second signal(s) and a third clock signal, and producing one or more output signal(s) of said digital circuitry, said second clocked element being switchable by said third clock signal between a second responsive state, in which the second clocked element changes said one or more output signal(s) in response to a change in said one or more second signal(s) to change the one or more output signal(s) of said digital circuitry, and a second non-responsive state in which no change in said one or more output signal(s) occurs, and
• a clock generating circuitry generating the second and third clock signals from the first clock signal, the second clock signal being delayed relative to the first clock signal by a preselected delay time and said third clock signal being delayed relative to the first clock signal by less than said preselected delay time such that in each cycle the first clocked element enters said first non-responsive state before the end of said predetermined processing operation, and said second clocked element enters said second responsive state when the first clocked element is in said first non-responsive state;
• and
• an analog circuitry connected to said digital circuitry for receiving therefrom said one or more output signal(s) and operable to produce one or more analog signal(s) in dependence upon the received one or more output signal(s).

A digital-analog converter circuit, comprising:

• a digital circuit to perform a series of processing cycles, comprising:
• an input signal processing circuit clocked by a first clock signal, inputting one or more first signal(s), performing a predetermined processing operation of the one or more first signal(s), and outputting a first output signal,
• a first latch circuit clocked by a second clock signal, inputting the first output signal, and outputting a second output signal,
• a second latch circuit clocked by a third clock signal, and inputting the second output signal from the first latch circuit, and
• a clock generating circuit generating the second and the third clock signals from the first clock signal,
• the second clock signal being delayed relative to the first clock signal by a predetermined delay time, and a rising edge of the third clock signal edge occurring at substantially the same time as a rising edge of the first clock signal and a falling edge of the third clock signal occurring at substantially the same time as a rising edge of the second clock signal;
• and
• an analog circuit connected to said digital circuit receiving therefrom one or more output signal(s) and operable to produce one or more analog signal(s) in dependence upon said one or more output signal(s).

A digital-analog converter circuit, comprising:

• a digital circuit to perform a series of processing cycles, comprising:
• an input signal processing circuit clocked by a first clock signal, inputting one or more first signal(s), and performing a predetermined processing operation on the one or more first signal(s), and outputting a first output signal,
• a first latch circuit clocked by a second clock signal and inputting the first output signal,
• a second latch circuit clocked by a third clock signal and inputting an output signal from the first latch circuit, and
• a clock generating circuit generating the second and third clock signals from the first clock signal, the second clock signal being delayed relative to the first clock signal by a predetermined delay time, a rising edge of the third clock signal without a substantial delay time relative to a rising edge of the first clock signal or with a shorter delay time than the delay time of the second clock signal and making the second latch circuit enter a responsive state during a non-responsive state of the first latch circuit;
• and
• an analog circuit connected to said digital circuit receiving therefrom one or more output signal(s) to produce one or more analog signal(s) in dependence upon said one or more output signal(s) received from the digital circuit.

A digital-analog converter circuit, comprising:

• a digital circuit performing a series of processing cycles, comprising:
• a digital input circuit receiving a plurality of digital signals in response to a first clock signal,
• a delay element receiving the first clock signal and outputting a delayed clock signal,
• a clock generating circuit receiving the first clock signal and generating a second clock signal, produced from the delayed clock signal, and a third clock signal, produced from the first clock signal and the delayed clock signal,
• a first latch circuit, coupled to the digital input circuit, receiving an output signal from the digital input circuit in response to the second clock signal, and
• a second latch circuit, coupled to the first latch circuit, receiving an output signal from the first latch circuit in response to the third clock signal;
• and
• an analog circuit connected to said digital circuit, receiving therefrom one or more output signal(s), and producing one or more analog signal(s) in dependence upon the received one or more output signal(s) from the digital circuit.

A digital-analog converter circuit comprising:

• a digital circuit to perform a series of processing cycles, comprising:
• an input signal processing circuit clocked by a first clock signal, inputting one or more first signal(s), and performing a predetermined processing operation on the first signal(s), and outputting a first output signal;
• a clock generating circuit generating second and third clock signals from the first clock signal, the second clock signal being delayed relative to the first clock signal by a first preselected delay time and the third clock signal being delayed relative to the first clock signal by a second preselected delay time;
• a first latch circuit being switchably clocked by the second clock signal;
• a second latch circuit clocked by the third clock signal, wherein the first latch circuit and the second latch circuit operate between a responsive state and a non-responsive state by turns;
• and
• an analog circuit connected to said digital circuit receiving therefrom one or more output signal(s) to produce one or more analog signal(s) in dependence upon one or more output signal(s) from the digital circuit.