Redundant telecommunication system using memory equalization apparatus and method of operation

A redundant, high-availability system of processor-based components, comprising:

• an active component;
• a standby component;
• and
• a system for memory equalization between the active and standby components comprising:
• counterpart memories within the active and standby components each containing data elements stored within one of a plurality of defined memory segments mapped to addresses within both of the counterpart memories, wherein the data elements within the memory segments may be selectively changed;
• a direct memory access circuit within each of the active and standby components, the direct memory access circuit within the active component capable of automatically copying memory segments from the memory within the active component to a queue within the active component without utilizing a processor within the active component changing the memory segments within the active component and the direct memory access circuit within the standby component capable of automatically copying memory segments from a queue within the standby component to the memory within the standby component without utilizing a processor within the standby component changing the memory segments within the standby component;
• a data link coupling to the queue within the active component to the queue within the standby component, wherein each of the plurality of memory segments is structured to form a data packet which may be transmitted without internal changes over the data link;
• and
• a control within the active component preventing the memory segments within the memory in the active component from receiving changes to the data elements contained therein faster than transfer of data elements within the memory segments over the data link.

For use in a redundant, high-availability system of processor-based components, a method of memory equalization comprising the steps of:

• selectively changing data elements each stored within one of a plurality of defined memory segments contained within a memory;
• automatically copying memory segments from the memory to a queue utilizing a direct memory access circuit and without utilizing a processor changing the memory segments;
• transferring memory segments over a data link coupled to the queue, wherein each of the plurality of memory segments is structured to form a data packet which may be transmitted without internal changes over the data link;
• and
• inhibiting the memory segments from receiving changes to the data elements contained therein faster than transfer of data elements within the memory segments over the data link.