Reduced pin gigabit media independent interface
AssigneeMarvell International Ltd.
InventorWilliam Lo
Life of this patent
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Abstract
A system for encoding signals for a network device includes an encoder configured to encode a transmit control signal. The transmit control signal includes a transmit enable signal in a first half of a cycle of a clock signal, and a transmit error signal in a second half of the cycle of the clock signal. The system includes a control signal transmitter configured to transmit the encoded transmit control signal. The system includes a data signal transmitter configured to transmit a transmit data signal. When neither the transmit enable signal nor the transmit error signal is in a first state in a respective half of the cycle of the clock signal, the transmit data signal includes signaling data.
Claims51
A method of encoding signals for a network device, comprising the steps of:
- encoding a transmit control signal,
- wherein the transmit control signal comprises a transmit enable signal in a first half of a cycle of a clock signal, and a transmit error signal in a second half of the cycle of the clock signal;
- forming a transmit data signal,
- wherein when neither the transmit enable signal nor the transmit error signal is in a first state in a respective half of the cycle of the clock signal, the transmit data signal comprises signaling data;
- transmitting the encoded transmit control signal;
- and
- transmitting the transmit data signal.
A method of decoding signals for a network device, comprising the steps of:
- receiving a receive control signal;
- decoding the receive control signal,
- wherein the receive control signal comprises a receive data valid signal in a first half of a cycle of a clock signal, and a receive error signal in a second half of the cycle of the clock signal;
- and
- receiving a receive data signal,
- wherein when neither the receive data valid signal nor the receive error signal is in a first state in a respective half of the cycle of the clock signal, the receive data signal comprises signaling data.
A transceiver, comprising:
- an encoder,
- wherein the encoder is configured to encode a transmit control signal, and
- wherein the transmit control signal comprises a transmit enable signal in a first half of a cycle of a clock signal, and a transmit error signal in a second half of the cycle of the clock signal;
- a control signal transmitter,
- wherein the control signal transmitter is configured to transmit the encoded transmit control signal;
- and
- a data signal transmitter,
- wherein the data signal transmitter is configured to transmit a transmit data signal, and
- wherein when neither the transmit enable signal nor the transmit error signal is in a first state in a respective half of the cycle of the clock signal, the transmit data signal comprises signaling data.
A transceiver, comprising:
- a control signal receiver,
- wherein the control signal receiver is configured to receive a receive control signal;
- a decoder in communication with the control signal receiver,
- wherein the decoder is configured to decode the receive control signal, and
- wherein the receive control signal comprises a receive data valid signal in a first half of a cycle of a clock signal, and a receive error signal in a second half of the cycle of the clock signal;
- and
- a data signal receiver,
- wherein the data signal receiver is configured to receive a receive data signal, and
- wherein when neither the receive data valid signal nor the receive error signal is in a first state in a respective half of the cycle of the clock signal, the receive data signal comprises signaling data.
An Ethernet transceiver, comprising:
- an encoder configured to form a transmit control signal,
- wherein the transmit control signal comprises in a first half of a cycle of a clock signal a transmit enable signal, and comprises in a second half of the cycle of the clock signal a transmit error signal;
- a control signal transmitter configured to transmit the transmit control signal encoded by the encoder;
- and
- a data signal transmitter configured to transmit a data signal.
An Ethernet transceiver, comprising:
- a control signal receiver configured to receive a receive control signal;
- a decoder configured to decode the receive control signal,
- wherein the receive control signal comprises in a first half of a cycle of a clock signal one of a receive data valid signal and a carrier sense signal, and comprises in a second half of the cycle of the clock signal a receive error signal;
- and
- a data signal receiver configured to receive a data signal.
Dependencies are inferred from the claim text.