Cell stream replicating device

A method of operating a digital traffic replicating device for use in testing a multi-port communication device, comprising the steps of:

• receiving an input digital traffic stream;
• and
• generating a plurality of output digital traffic streams from the input digital traffic stream, wherein
• a phase delay is introduced of at least one steam of the plurality of output digital traffic streams;
• said phase delay is determined from a ratio utilizing a buffer length associated with at least one stream;
• transmission of said at least one of the plurality of output digital traffic streams begins at a time between boundaries of time units of a transmission rate associated with said input digital traffic stream;
• and
• the plurality of output digital traffic streams have traffic patterns which are replicas of the input digital traffic stream;
• and

An apparatus for generating digital traffic for use in testing a multi-port communication device, said apparatus comprising:

• a reference pattern generator generating a reference pattern defining a digital traffic pattern;
• a traffic stream replicating device generating a plurality of traffic streams replicated from the reference pattern;
• and
• a phase delay module providing respective phase delays among the plurality of traffic streams utilizing a series of buffers, such that transmission of at least one traffic stream of said plurality of traffic streams is provided with a phase delay based on a length of a buffer of said buffers associated with said at least one traffic stream and begins at a time between boundaries of time units of a transmission rate associated with said plurality of traffic streams, wherein the plurality of traffic streams load respective input ports of the communication device.

A digital data stream replicating device, comprising:

• an input port for receiving an input continuous digital data stream comprising input data blocks at an input transmission rate;
• a traffic replicator to replicate broadcast means for replicating the input continuous digital data stream into N streams of replicated continuous digital data streams;
• N output ports for transmitting the plurality of replicated continuous digital data streams at output transmission rates, each output transmission rate at least equal to the input transmission rate;
• and
• a delay module providing a predetermined delay for each replicated continuous digital data stream of the plurality of replicated digital data streams with respect to the input continuous digital data stream, such that transmission of at least one stream of said each replicated continuous digital data stream has a phase delay determined from a length of a buffer associated with at least one stream and begins at a time between boundaries of time units of a transmission rate associated with said input digital traffic.

A digital data stream replicating device for providing data traffic input patterns to a communication device, comprising:

• an input port for receiving a continuous digital data stream comprising input data blocks at an input transmission rate;
• a memory;
• N output ports, each having an output transmission rate at least equal to the input transmission rate;
• a traffic processor connected between the input port and the N output ports, for providing N first-in first-out logical buffers in the memory and associating each of the input data blocks of the continuous digital data stream with each one of the N logical buffers so as to replicate the input data blocks thereacross, each logical buffer being associated with only one of the output ports;
• and
• a scheduler to forward data blocks associated with a given logical buffer through its corresponding output port when the given logical buffer is full, such that transmission of said data blocks begins at a time between boundaries of time units of a transmission rate associated with said corresponding output port and a phase delay associated with said transmission of said data blocks is determined from at least a length of said logical buffer.

A performance testing device, comprising:

• a traffic generator for generating a continuous digital data stream;
• an input port for receiving the continuous digital data stream at an input transmission rate;
• a broadcaster for replicating the input digital data stream N times;
• N output ports for transmitting each such replicated digital data stream through a separate output port at an output transmission rate at least equal to the input transmission rate;
• and
• a delay module for introducing a predetermined relative delay for each said transmitted digital data stream with respect to the input digital data stream, such that transmission of at least one stream of said each said transmitted digital data stream begins at a time between boundaries of time units of a transmission rate associated with said each transmitted digital data stream and has a phase delay determined by at least a length of a buffer associated with said at least one stream.

A performance testing device, comprising:

• a the generator for generating a continuous digital data stream;
• an input port for receiving the continuous digital data stream comprising input data blocks at an input transmission rate;
• a memory;
• N output ports, each having an output transmission rate at least equal to the input transmission rate;
• a traffic processor connected between the input port and the N output ports, providing N first-in first-out logical buffers in the memory and associating each of the input data blocks of the continuous digital data stream with each one of the N logical buffers so as to replicate the input data blocks thereacross, each logical buffer being associated with only one of the output ports;
• and
• a scheduler for forwarding data blocks associated with a given logical buffer through its corresponding output port when the given logical buffer is full, such that transmission of said data blocks begins at a time between boundaries of time units of an output transmission rate associated with transmission of said data blocks and said transmission has a phase delay determined by at least a length of said logical buffer.

A performance testing device, comprising:

• a traffic generator for generating a continuous digital data stream;
• an input port for receiving the continuous digital data stream comprising input data blocks at an input transmission rate;
• a memory;
• N output ports, each having an output transmission rate at least equal to the input transmission rate;
• a traffic processor connected between the input port and the N output ports for establishing N first-in first-out logical buffers in the memory and associating each of the input data blocks of the continuous digital data stream with each one of the N logical buffers so as to replicate the input data blocks thereacross, each logical buffer being associated with only one of the output ports;
• and
• a scheduler for forwarding data blocks associated with a given logical buffer through its corresponding output port when the given logical buffer is full such that transmission of said data blocks begins at a time between boundaries of time units of an output transmission rate associated with transmission of said data blocks
• wherein one of said N first-in first-out logical buffers is a given size and at least another of said N first-in first-out logical buffers is a different size than said given size.