Latency control circuit and method of latency control
AssigneeSamsung Electronics Co., Ltd.
InventorsSang-bo Lee, Ho-young Song
Life of this patent
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Abstract
The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.
Claims8
A latency circuit for generating a latency signal that controls output of data from a memory device, comprising:
- pointer generating circuits creating a relationship between first pointers for identifying a time of read information receipt and second pointers identifying when to generate a latency signal with respect to the first pointers;
- and
- a signal generating circuit generating the latency signal based on the first and second pointers.
A method of generating a latency signal that controls output of data from a memory device, comprising:
- creating a relationship between first pointers for identifying a time of read information receipt and second pointers identifying when to generate a latency signal with respect to the first pointers;
- and
- generating the latency signal based on the first and second pointers.
Dependencies are inferred from the claim text.