Refreshing dynamic memory cells in a memory circuit and a memory circuit
AssigneeInfineon Technologies AG
InventorManfred Dobler
Life of this patent
Estimating the term…
Abstract
Methods and apparatus for refreshing a dynamic memory cell in a memory circuit are provided, wherein the required time between refresh operations may be increased by increasing the potential difference between a high charge potential and common center potential used during a refresh mode relative to the potential difference between the high charge potential and the common center potential used during read or write modes.
Claims19
A method for refreshing a dynamic memory cell in a memory circuit, the memory cell being arranged at a word line and a bit line of a bit line pair, comprising:
- during read-out of the memory cell, activating the word line and amplifying, with a sense amplifier, a charge difference brought about thereby on the bit lines to generate a high charge potential and a low charge potential;
- after the readout, charging the potentials of the bit lines to a first center potential;
- during refresh of the memory cell, activating the word line and amplifying, with the sense amplifier, the charge potentials of the bit lines, depending on charge information of the memory cell, to generate a high refresh potential and a low refresh potential;
- and
- after the refresh, charging the potentials of the bit lines to a second center potential, wherein the potential difference between the high refresh potential to which the sense amplifier drives the bit lines during refresh and the second center potential is greater than the potential difference between the high charge potential to which the sense amplifier drives the bit lines during readout and the first center potential.
A memory circuit, comprising:
- a memory cell array with a memory cell arranged at a word line and a bit line pair;
- a refresh circuit for generating signals to refresh the memory cell;
- a charge equalization circuit to charge the bit lines to a common center potential after a read-out or refresh of the memory cell;
- a sense amplifier in order to separate a charge difference between the bit lines into a high charge potential and a low charge potential when the wordline is activated during a read-out or refresh of the memory;
- and
- voltage control means for varying the potential difference between the high charge potential and the common center potential, wherein the potential difference between the high charge potential and the common center potential during a refresh of the memory cell is greater than the potential difference between the high charge potential and the common center potential during a read-out of the memory cell.
A memory circuit, comprising:
- a memory cell array with a memory cell arranged at a word line and a bit line pair;
- a refresh circuit for generating signals to refresh the memory cell;
- a charge equalization circuit to charge the bit lines to a common center potential after a read-out or refresh of the memory cell;
- a sense amplifier in order to separate a charge difference between the bit lines into a high charge potential and a low charge potential when the wordline is activated during a read-out or refresh of the memory;
- first and second potential sources, wherein the first potential source is greater than the second potential source;
- and
- a voltage control circuit configured to provide the sense amplifier with the high charge potential from the first potential source during refresh of the memory cell and from a second high potential source during read-out of the memory cell.
Dependencies are inferred from the claim text.