Storage device employing a flash memory

A storage device employing a flash memory, wherein said flash memory is divided into a plurality of physical sectors identified by physical addresses, wherein said flash memory carries out data write operation of write data from a host system into a sector of said plurality of physical sectors in response to a host logical address accompanied with said write data from said host system, said storage device includes:

• a memory controller which generates a physical address in response to said host logical address for said data write operation of said write data from said host system,
• wherein said memory controller carries out address translation from host logical addresses to physical addresses,
• wherein said memory controller carries out a current data write operation in which current write data from said host system is written into a selected one sector of said plurality of physical sectors identified by a current physical address which is converted by said memory controller from a current host logical address, and said memory controller carries out a succeeding data write operation in which succeeding write data from said host system is written into a selected another one sector of said plurality of physical sectors identified by the succeeding physical address which is converted by said memory controller from a succeeding host logical address that is identical to said current host logical address, and wherein said data write operation is carried out within said storage device even though said selected one sector of said plurality of physical sectors is not defective and is usable before said succeeding data write operation, so that even when data of a specific host logical address are frequently rewritten from said host system, the same physical address is not always used in said storage device, but different physical addresses, which correspond to said same specific host logical address and are generated by said memory controller, are used, thereby leveling of wears by erasures of said plurality of physical sectors,
• wherein said memory controller seeks an old physical sector of said specific host logical address in which unnecessary data is written and carries out an erase operation of unnecessary data in said old physical sector among said plurality of physical sectors,
• wherein said memory controller stores a new correspondence between a new physical sector and the specific host logical address within a table for said address translation, said new physical sector is identified by a new physical address translated from said same specific host logical address by said memory controller,
• wherein said memory controller is provided with a volatile memory store address data, and
• wherein said address data of said volatile memory is originated from an address information stored in said flash memory by said controller at start of system operation, and then said memory controller accesses said flash memory based said address data of said volatile memory.

A storage device employing a nonvolatile semiconductor flash memory, wherein said nonvolatile semiconductor flash memory is divided into a plurality of physical sectors identified by physical addresses, wherein said flash memory carries out data write operation of a write data from a host system into a sector of said plurality of physical sectors in response to a host logical address accompanied with said write data from said host system, said storage device includes:

• a memory controller which generates a physical address in response to said host logical address for said data write operation of said write data from said host system,
• wherein said memory controller carries out address conversion from host logical addresses to physical addresses,
• wherein said memory controller carries out a current data write operation in which current write data from said host system is written into a selected one sector of said plurality of physical sectors identified by a current physical address which is converted by said memory controller from a current host logical address, and said memory controller carries out a succeeding data write operation in which succeeding write data from said host s stem is written into a selected another one sector of said plurality of physical sectors identified by the succeeding physical address which is converted by said memory controller from a succeeding host logical address that is identical to said current host logical address, and wherein said succeeding data write operation is carried out within said storage device even though said selected one sector of said plurality of physical sectors is not defective and is usable before said succeeding data write operation, so that even when data of a specific host logical address are frequently rewritten from said host system, the same physical address is not always used in said storage device, but different physical addresses, which correspond to said same specific host logical address and are generated by said memory controller, are used to carry out data write operations of write data from said host system into different physical sectors of said flash memory in response to said same specific host logical address,
• wherein said memory controller seeks an old physical sector of said specific host logical address in which unnecessary data is written and carries out an erase operation of unnecessary data in said old physical sector among said plurality of physical sectors,
• wherein said memory controller stores a new correspondence between a new physical sector and the specific host logical address within an address table for said address conversion, said new physical section is identified by a new physical address converted from said same specific host logical address by said memory controller,
• wherein said memory controller is provided with a volatile memory to store address data, and
• wherein said address data of said volatile memory is originated from an address information stored in said nonvolatile semiconductor flash memory by said controller at start of system operation, and then said memory controller accesses said nonvolatile semiconductor flash memory based upon said address data of said volatile memory.