Semiconductor memory device with common I/O type circuit configuration achieving write before sense operation
AssigneeRenesas Technology Corp.
InventorsTakayuki Gyohten, Masaru Haraguchi, Fukashi Morishita
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Abstract
A connection gate circuit includes first and second N channel MOS transistors connected in series between a first bit line of a pair of bit lines and a first global IO line of a pair of IO lines, and third and fourth N channel MOS transistors connected in series between a second bit line of the pair of bit lines and a second global IO line of the pair of IO lines. The first and second N channel MOS transistors have their gates receiving a sense amplifier activation signal activating a sense amplifier. The third and fourth N channel MOS transistors have their gates receiving a column selection signal.
Claims9
A semiconductor memory device comprising:
- a memory cell storing data;
- a pair of bit lines connected to said memory cell;
- a sense amplifier provided corresponding to said pair of bit lines and activated in response to a sense amplifier activation signal;
- a pair of I/O lines transmitting said data input/output to/from said memory cell via said pair of bit lines;
- and
- a connection gate circuit provided between said pair of bit lines and said pair of I/O lines and electrically connecting said pair of bit lines to said pair of I/O lines when said sense amplifier activation signal and a column selection signal selecting said pair of bit lines are both activated;
- wherein
- said connection gate circuit includes first and second gates connected in series between said pair of bit lines and said pair of I/O lines,
- said first gate conducts in response to said sense amplifier activation signal, and
- said second gate conducts in response to said column selection signal.
A semiconductor memory device comprising:
- a memory cell storing data;
- a pair of bit lines connected to said memory cell;
- a sense amplifier provided corresponding to said pair of bit lines and activated in response to a sense amplifier activation signal;
- a pair of I/O lines transmitting said data input/output to/from said memory cell via said pair of bit lines;
- a connection gate circuit provided between said pair of bit lines and said pair of I/O lines and electrically connecting said pair of bit lines to said pair of I/O lines when said sense amplifier activation signal and a column selection signal selecting said pair of bit lines are both activated;
- and
- a logic gate circuit activating its output signal when said sense amplifier activation signal and said column selection signal are activated;
- wherein
- said connection gate circuit includes a gate conducting in response to said output signal from said logic gate circuit.
A semiconductor memory device comprising:
- a memory cell storing data;
- a pair of bit lines connected to said memory cell;
- a sense amplifier provided corresponding to said pair of bit lines and activated in response to a sense amplifier activation signal;
- a pair of I/O lines transmitting said data input/output to/from said memory cell via said pair of bit lines;
- a connection gate circuit provided between said pair of bit lines and said pair of I/O lines and electrically connecting said pair of bit lines to said pair of I/O lines when said sense amplifier activation signal and a column selection signal selecting said pair of bit lines are both activated;
- and
- a logic gate circuit activating its output signal when said sense amplifier activation signal and said column selection signal are activated;
- wherein
- said connection gate circuit includes a gate conducting in response to said output signal from said logic gate circuit;
- wherein
- said connection gate circuit further includes another gate conducting in response to a write mask signal, and
- said gate and said another gate are connected in series between said pair of bit lines and said pair of I/lines.
Dependencies are inferred from the claim text.