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US 7,064,991 B2Granted
Semiconductor storage device
AssigneeElpida Memory, Inc.
InventorKazunori Maeda
Life of this patent
Estimating the term…
Abstract
A semiconductor storage device includes command decoder for decoding an input command to output a decoded result and for simultaneously outputting A and B bank activation signal for activating said first and second banks, during a parallel test; a set of bank A control circuits for generating a control signal for a bank A based on a bank A activating signal, a selector circuit receiving a bank B activation signal output from the command decoder and the control signal for a bank A, for selecting outputting a bank B activating signal during the normal operation and for selecting and outputting the control signal for a bank A during parallel test, and a set of bank B control circuits receiving the output from the selector circuit to generate a control signal for the bank B.
Claims15
A semiconductor storage device comprising:
- a plurality of banks, each having a cell array;
- a command decoder for decoding an input command to output a decoded result;
- a plurality of bank control circuits, each provided for each of said banks and each generating and outputting a control signal for the associated bank based on a bank activating signal output from said command decoder during normal operation;
- and
- a circuit for performing control during parallel test in such a manner that the start timings of activating said plural banks will be offset from one bank to the next, based on the bank activating signal output from said command decoder and a signal output from at least one of said bank control circuits with a delay of a preset time as from the activation timing of said bank activating signal.
2 more elements
A semiconductor storage device comprising:
- first to n'th banks, each having a cell array, n being a preset integer not less than 2;
- a command decoder for decoding an input command to output a decoded result;
- and
- first to n'th bank controlling circuits for generating and outputting control signals for said first to n'th banks respectively,
- said command decoder simultaneously outputting first to n'th bank activating signals activating said first to n'th banks during a parallel test,
- said first bank controlling circuit generating the control signal for said first bank based on said first bank activating signal from said command decoder;
- the semiconductor storage device further comprising
- an i'th selection circuit associated with an (i+1)st bank control circuit, i being an integer not less than 1 and not larger than (n−1),
- said i'th selection circuit receiving the control signal for an i'th bank, output from an i'th bank controlling circuit, and an (i+1)st bank activation signal, output from said command decoder,
- said i'th selection circuit selecting and outputting the (i+1)st bank activation signal, output from said command decoder, during the normal operation,
- said i'th selection circuit selecting and outputting a control signal for an i'th bank, output from an i'th bank control circuit, as the (i+1)st bank activation signal, during the parallel test;
- said (i+1)st bank control circuit, receiving said (i+1)st bank activation signal output from said i'th selection circuit and generating a control signal for the (i+1)st bank.
9 more elements
A semiconductor storage device comprising:
- first and second banks, each having a cell array;
- a command decoder for decoding an input command to output a decoded result,
- said command decoder simultaneously outputting first and second bank activation signal for activating said first and second banks, during a parallel test;
- a first bank control circuit, receiving said first bank activating signal output from said command decoder, and generating a control signal for said first bank;
- a selection circuit, receiving as inputs said second bank activation signal, output from said command decoder, and the control signal for said first bank, output from said first bank control circuit, selecting and outputting said second bank activating signal, during the normal operation, and selecting and outputting said first bank activating signal, during the parallel test;
- and
- a second bank controlling circuit, receiving a signal output from said selection circuit as a second bank activating signal, and generating a control signal for said second bank.
4 more elements
A semiconductor storage device comprising:
- first to fourth banks, each having a cell array;
- a command decoder for decoding an input command to output a decoded result,
- said command decoder simultaneously outputting first to fourth bank activation signals for activating said first to fourth banks, during parallel test;
- a first bank controlling circuit, receiving said first bank activation signal output from said command decoder, and generating a control signal for said first bank;
- a first selection circuit, receiving said second bank activation signal, output from said command decoder, and the control signal for said first bank, output from said first bank controlling circuit, selecting and outputting said second bank activating signal, during the normal operation, and selecting and outputting said control signal for said first bank, during the parallel test;
- a second bank controlling circuit, receiving a signal output from said first selection circuit as a second bank activating signal, and generating a control signal for the second bank;
- a second selection circuit, receiving said third bank activation signal, output from said command decoder, and the control signal for said second bank, output from said second bank controlling circuit, selecting and outputting said third bank activating signal, during the normal operation, and selecting and outputting said control signal for said second bank, during the parallel test;
- a third bank controlling circuit, receiving a signal output from said second selection circuit as a third bank activating signal, and generating a control signal for the third bank;
- a third selection circuit, receiving said fourth bank activation signal, output from said command decoder, and the control signal for said third bank, output from said third bank controlling circuit, selecting and outputting said fourth bank activating signal, during the normal operation, and selecting and outputting said control signal for said third bank, during the parallel test;
- and
- a fourth bank controlling circuit, receiving a signal output from said third selection circuit as a fourth bank activating signal, and generating a control signal for the fourth bank.
8 more elements
Dependencies are inferred from the claim text.