Method and apparatus for implementing multiple column redundancy for memory

A method for implementing multiple memory column redundancy within an individual memory array, the method comprising:

• internally partitioning a plurality of memory array elements into at least a pair of subcolumn elements;
• configuring at least two spare memory elements at a size corresponding to one of said subcolumn elements;
• configuring an input redundancy multiplexing stage and an output redundancy multiplexing stage for steering around one or more defective memory array elements;
• and
• implementing an additional, external multiplexing stage with respect to said input redundancy multiplexing stage and said output redundancy multiplexing stage through an input bit decoding stage and an output bit decoding stage.

An apparatus for implementing multiple memory column redundancy, within an individual memory array, comprising:

• a plurality of memory array elements internally partitioned into at least a pair of subcolumn elements;
• at least a pair of spare memory elements, each of said spare memory element configured at a size corresponding to one of said subcolumn elements;
• an input redundancy steering stage comprising a plurality of multiplexing devices corresponding to the structure of said internally partitioned memory array elements and said pair of spare memory elements;
• an output redundancy steering stage comprising a plurality of multiplexing devices corresponding to the structure of said internally partitioned memory array elements, said input and output steering redundancy steering stages configured for steering around one or more defective memory array elements;
• and
• an input bit decoding stage and an output bit decoding stage configured for implementing an additional, external multiplexing stage with respect to said input redundancy steering stage and said output redundancy steering stage.