Circuit and method for reducing leakage current in a row driver circuit in a flash memory during a standby mode of operation

A row driver, comprising:

• a first coupling means having a first terminal adapted to receive a supply voltage, a second terminal coupled to an output node adapted to be coupled to a word line, and a control terminal adapted to receive an input signal for coupling or isolating the first and second terminals responsive to the input signal;
• a second coupling means having a first terminal, a second terminal coupled to the output node, and a control terminal adapted to receive the input signal for coupling or isolating the first and second signal terminals responsive to the input signal;
• and
• an isolation means adapted to receive the reference voltage and coupled to the first terminal of the second coupling means, and adapted to receive a test mode signal for applying the reference voltage on the first terminal of the second coupling means when the test mode signal goes inactive and for presenting a high impedance on the first terminal of the second coupling means when the test mode signal goes active.

A memory device, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
• the memory-cell array including a plurality of word lines;
• and
• a plurality of row drivers, each row driver coupled to an associated word line in the memory-cell array and coupled to the address decoder to receive a row activation signal, and the row driver being coupled to the control circuit to receive a test mode signal, each row driver being operable in an active mode responsive to the test mode signal going inactive to couple the associated word line to either a first or a second voltage source responsive to the corresponding row activation signal, and being operable in a standby mode responsive to the test mode signal going active to present a high impedance to the corresponding word line.

A computer system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a memory device coupled to the processor, the memory device comprising,
• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
• the memory-cell array including a plurality of word lines;
• and
• a plurality of row drivers, each row driver coupled to an associated word line in the memory-cell array and coupled to the address decoder to receive a row activation signal, and the row driver being coupled to the control circuit to receive a test mode signal, each row driver being operable in an active mode responsive to the test mode signal going inactive to couple the associated word line to either a first or a second voltage source responsive to the corresponding row activation signal, and being operable in a standby mode responsive to the test mode signal going active to present a high impedance to the corresponding word line.