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US 7,064,981 B2Granted
NAND string wordline delay reduction
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
Estimating the term…
Abstract
An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line capacitive coupling to reduce word line selection delay by driving the adjacent word lines to a higher initial voltage and then reducing it to the final target voltage. As the capacitive coupling in between the NAND word lines is a larger effect when the voltages are being lowered, this has the effect of damping out the voltage initially induced in the lower voltage word line by the rising voltages on the adjacent word lines, reducing the overall selection time.
Claims31
A method of operating a NAND architecture memory array, comprising:
- applying an initial read pass voltage to one or more unselected word lines;
- applying a read select voltage to a selected word line;
- and
- reducing the initial read pass voltage on the one or more unselected word lines to a final read pass voltage.
1 more element
A method of read accessing in a memory array, comprising:
- applying an initial voltage to one or more unselected word lines;
- applying a read select voltage to a selected word line;
- and
- reducing the initial voltage on the one or more unselected word lines to a final voltage.
1 more element
A method of damping capacitively coupled voltage in a memory array, comprising:
- applying an initial elevated voltage to one or more first signal lines, where the one or more first signal lines are adjacent to a second signal line;
- applying a target voltage to the second signal line;
- and
- reducing the initial elevated voltage on the one or more first signal lines to a final elevated voltage.
1 more element
A NAND architecture Flash memory array, comprising:
- a NAND architecture memory array having a plurality of non-volatile memory cells arranged in rows and columns in a plurality of erase blocks, wherein the plurality of memory cells are serially coupled source to drain into a plurality of NAND memory cell strings;
- a plurality of word lines, wherein each word line is coupled to one or more gates of a row of the memory cells;
- a plurality of bitlines, wherein each bitline is coupled to a first memory cell of one or more strings through a drain control gate transistor;
- at least one source line, wherein the at least one source line is coupled to a last memory cell of one or more strings through a source control gate transistor;
- a row decoder coupled to the plurality of word lines;
- and
- a control circuit coupled to the row decoder, wherein the control circuit is adapted to place an elevated initial read pass voltage on one or more unselected word lines and then reduce the read pass voltage.
4 more elements
A NAND architecture Flash memory device, comprising:
- a NAND architecture memory array having a plurality of non-volatile memory cells arranged in rows and columns in a plurality of erase blocks, wherein the plurality of memory cells are serially coupled source to drain into a plurality of NAND memory cell strings;
- a row decoder coupled to a plurality of word lines, wherein each word line is coupled to one or more gates of a row of the memory cells;
- a plurality of bitlines, wherein each bitline is coupled to a first memory cell of one or more strings through a drain control gate transistor;
- at least one source line, wherein the at least one source line is coupled to a last memory cell of one or more strings through a source control gate transistor;
- and
- a control circuit coupled to the row decoder, wherein the control circuit is adapted to place an elevated initial read pass voltage on one or more unselected word lines and then reduce the read pass voltage to a target read pass voltage.
3 more elements
A system, comprising:
- a host coupled to a Flash memory device, wherein the Flash memory device comprises,
- a NAND architecture memory array having a plurality of non-volatile memory cells arranged in rows and columns in a plurality of erase blocks, wherein the plurality of memory cells are serially coupled source to drain into a plurality of NAND memory cell strings;
- a row decoder coupled to a plurality of word lines, wherein each word line is coupled to one or more gates of a row of the memory cells;
- a plurality of bitlines, wherein each bitline is coupled to a first memory cell of one or more strings through a drain control gate transistor;
- at least one source line, wherein the at least one source line is coupled to a last memory cell of one or more strings through a source control gate transistor;
- and
- a control circuit coupled to the row decoder, wherein the control circuit is adapted to place an elevated initial read pass voltage on one or more unselected word lines and then reduce the read pass voltage to a target read pass voltage.
4 more elements
A Flash memory device, comprising:
- a NAND architecture memory array having a plurality of non-volatile memory cells arranged in rows and columns and having a means for coupling into a plurality of NAND memory cell strings;
- a means for coupling a plurality of word lines to one or more gates of a row of the memory cells;
- a means for coupling a plurality of bitlines to a drain of a first memory cell of one or more strings;
- a means for coupling at least one source line to a source of a last memory cell of one or more strings;
- a means for coupling a row decoder to the plurality of word lines;
- and
- a means for coupling a control circuit to the row decoder, wherein the control circuit is adapted to have a means for placing an elevated initial read pass voltage on one or more unselected word lines and a means for then reducing the read pass voltage to a target read pass voltage.
4 more elements
Dependencies are inferred from the claim text.